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SPIE: sparse partial inductance extraction

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 137 - 140

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Zhijiang He	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Mustafa Celik	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Lawrence Pileggi	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 8, Citation Count: 19

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ABSTRACT

Extracting the inductance of complex interconnect topologiesis a formidable task, and simulating the resulting dense partialinductance matrix is even more difficult. Furthermore, it is wellknown that simply discarding smallest terms to sparsify the inductancematrix can render the partial inductance matrix indefiniteand result in an unstable circuit model. In this paper, wedescribe a methodology for incrementally generating a sparsepartial inductance matrix based on using moments about s=0 todetermine when a sufficient number of mutual inductances havebeen captured. The minimally required mutual inductances areextracted for a provably stable model.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F.W.Grover, Inductance Calculations, Dover Publications, New York, 1946.
	2	M.Kamon, M.J.Tsuk, and J.K.White, "FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program", IEEE Transactions on Microwave Theory and Techniques, 42, No. 9, Sept. 1994.
	3	Byron Krauter , Lawrence T. Pileggi, Generating sparse partial inductance matrices with guaranteed stability, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.45-52, November 05-09, 1995, San Jose, California, United States
	4	L.Pillage, R.Rohrer, C. Visweswariah, "Electronic Circuit and System Simulation Methods," McGraw-Hill, Inc. 1994
	5	E.B.Rosa, "The Self and Mutual Inductance of Linear Conductors," Bulletin of the National Bureau of Standards, Vol. 4, pp. 301-344, 1908.
	6	A.E.Ruehli, "Inductance Calculations in a Complex Integrated Circuit Environment," IBM Journal of Research and Development, 16, No.5,470-481 (September 1972).
	7	A.E.Ruehli, "Equivalent Circuit Models for Three-Dimensional Multiconductor Systems," IEEE Trans. on MTT, Vol. MTT-22, No.3, March 1974.
	8	W.T.Weeks, L.L.Wu, M.F.McAllister, and A.Singh, "Resistive and Inductive Skin Effect in Rectangular Conductors," IBM Journal of Research and Development, 23, No.6, 652- 660 (November 1979).

CITED BY 19

	Hao Yu , Lei He, Vector potential equivalent circuit based on PEEC inversion, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Hao Ji , Anirudh Devgan , Wayne Dai, KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect, Proceedings of the 2001 conference on Asia South Pacific design automation, p.379-384, January 2001, Yokohama, Japan
	Haitian Hu , David T. Blaauw , Vladimir Zolotov , Kaushik Gala , Min Zhao , Rajendran Panda , Sachin S. Sapatnekar, A precorrected-FFT method for simulating on-chip inductance, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.221-227, November 10-14, 2002, San Jose, California
	Clement Luk , Tsung-Hao Chen , Charlie C.-P. Chen, Frequency-dependent reluctance extraction, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.792-797, January 27-30, 2004, Yokohama, Japan
	Guoan Zhong , Cheng-Kok Koh , Kaushik Roy, On-chip interconnect modeling by wire duplication, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.341-346, November 10-14, 2002, San Jose, California
	Hao Yu , Lei He , Zhenyu Qi , Sheldon X.-D. Tan, A wideband hierarchical circuit reduction for massively coupled interconnects, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Hao Ji , Qingjian Yu , Wayne Dai, SPICE compatible circuit models for partial reluctance K, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.786-791, January 27-30, 2004, Yokohama, Japan
	Mengsheng Zhang , Wenjian Yu , Yu Du , Zeyi Wang, An efficient algorithm for 3-D reluctance extraction considering high frequency effect, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Hemant Mahawar , Vivek Sarin , Weiping Shi, A solenoidal basis method for efficient inductance extraction, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	J. Jain , Cheng-Kok Koh , V. Balakrishnan, Fast simulation of VLSI interconnects, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.93-98, November 07-11, 2004
	Anirudh Devgan , Hao Ji , Wayne Dai, How to efficiently capture on-chip inductance effects: introducing a new circuit element K, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Tsung-Hao Chen , Clement Luk , Hyungsuk Kim , Charlie Chung-Ping Chen, INDUCTWISE: inductance-wise interconnect simulator and extractor, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.215-220, November 10-14, 2002, San Jose, California
	Rong Jiang , Charlie Chung-Ping Chen, SCORE: SPICE COmpatible Reluctance Extraction, Proceedings of the conference on Design, automation and test in Europe, p.20948, February 16-20, 2004
	Hui Zheng , Byron Krauter , Lawrence Pileggi, Electrical Modeling of Integrated-Package Power and Ground Distributions, IEEE Design & Test, v.20 n.3, p.24-31, May 2003
	Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw, On-chip inductance modeling and analysis, Proceedings of the 37th conference on Design automation, p.63-68, June 05-09, 2000, Los Angeles, California, United States
	Tao Lin , Michael W. Beattie , Lawrence T. Pileggi, On the efficacy of simplified 2D on-chip inductance models, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States
	Yi-Chang Lu , Mustafa Celik , Tak Young , Lawrence T. Pileggi, Min/max on-chip inductance models and delay metrics, Proceedings of the 38th conference on Design automation, p.341-346, June 2001, Las Vegas, Nevada, United States
	Kaveh Shakeri , James D. Meindl, Accelerated modeling of massively coupled RLC interconnects using the relative inductance extraction method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.745-754, June 2008