Bounds for BEM capacitance extraction

ABSTRACT

In this paper we prove that simply discarding conductors beyonda certain spacing during BEM capacitance extraction willresult in a lower bound on the self-capacitance calculations andan upper bound on the mutual capacitance calculations that liewithin that spacing. We prove that a potential-shift and truncatescheme can yield bounds opposite to those for the truncate onlycase; namely, an upper bound on the self capacitance and a lowerbound on the mutual capacitance that lies within the chosenspacing. The ease with which the upper and lower bounds arecalculated is shown, and their utility for selection of an optimalwindow size is described. A metal shell is also presented here thatresults in bounds similar to those of shift-truncate. We furtherpropose a new potential-shift function that yields increased approximationaccuracy compared to shift-truncate in many cases.

REFERENCES

• 1: Byron Krauter , Yu Xia , Aykut Dengi , Lawrence T. Pileggi, A sparse image method for BEM capacitance extraction, Proceedings of the 33rd annual conference on Design automation, p.357-362, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240586]
• 2: M. Beattie, M.S. Thesis, Carnegie Mellon University (Pittsburgh, USA), May 1997.
• 3: N. P. van der Meijs , A. J. van Genderen, An efficient finite element method for submicron IC capacitance extraction, Proceedings of the 26th ACM/IEEE conference on Design automation, p.678-681, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74502]
• 4: N. E van der Meijs, "Accurate and Efficient Layout Extraction", Doctoral dissertation, Technische Universiteit Delft (Netherlands), 1992.
• 5: K. Nabors, J. White, "FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program", IEEE Transactions on Computer-Aided Design. vol. 10, No. 11, November 1991.
• 6: C. Wei, R. F. Harrington, J. Mautz, T. Sarkar, "Multiconductor Transmission Lines in Multilayered Dielectric Media", IEEE Transactions on Microwave Theo17 and Techniques, vol. 32, No. 4, April 1984.
• 7: N. Arora, K. Raol, R. Schumann, L. Richardson, "Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits", IEEE Transactions on Computer-Aided Design. vol. 15, No. 1, January 1996.
• 8: D. Ling, A. Ruehli, "Interconnection Modeling", in: Circuit Analysis, Simulation and Design I Advances in CAD for VLSI Vol. 3, Part H (Chapter 11), Elsevier Science Publishers B.V. (North-Holland), 1987.

INDEX TERMS

Primary Classification:
  G. Mathematics of Computing
  G.1 NUMERICAL ANALYSIS

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS

General Terms:
Design, Measurement, Performance, Theory