Calculating worst-case gate delays due to dominant capacitance coupling

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Calculating worst-case gate delays due to dominant capacitance coupling

Full text

Pdf (98 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 46 - 51

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Florentin Dartu	Carnegie Mellon University, Department of ECE, Pittsburgh, PA
Lawrence T. Pileggi	Carnegie Mellon University, Department of ECE, Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 32, Citation Count: 48

Additional Information:

abstract references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/266021.266033 What is a DOI?

ABSTRACT

In this paper we develop a gate level model that allows us to determinethe best and worst case delay when there is dominant interconnectcoupling. Assuming that the gate input windows oftransition are known, the model can predict the worst and bestcase noise, as well as the worst and best case impact on delay. Thisis done in terms of a Ceff based gate model under general RCinterconnect loading conditions.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Bohr, "Interconnect scaling - the real limiter to high performance ULSI," Intl. Electronic Device Meeting, pp. 241- 244, 1995.
	2	H.B. Bakoglu, "Circuits, interconnections, and packaging for VLSI," Addison-Wesley, 1990.
	3	E Dartu, N. Menezes, L.T. Pileggi, "Performance computation for precharacterized CMOS gates with RC-loads," IEEE Transactions on CAD, vol. 15, pp. 544-553, May 1996.
	4	T. Sakurai, A.R. Newton, "Alpha-power model, and its application to CMOS inverter delay and other formulas," IEEE Journal of Solid State Circuits, vol. 25, pp. 584-594, April 1990.
	5	A.I. Kayssi, K.A. Sakallah, T.M. Burks, "Analytical transient response of CMOS inverters," IEEE Transactions on CAS-I, vol. 39, pp 42-45, January 1992.
	6	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	7	L.T. Pillage, R.A. Rohrer "Asymptotic waveform evaluation for timing analysis," IEEE Transactions on CAD, vol. 9, pp. 352-366, 1990.
	8	E Dartu, L.T. Pileggi, "Modeling signal waveshapes for empirical CMOS gate delay models," 6th Intl. Workshop PATMOS '96, pp. 57-66, Bologna, Italy, 1996
	9	Y. Miki, M. Abe, Y. Ogawa, "PCHECK: A delay tool for high performance LSI design," IEEE Custom Integrated Circuits Conference, pp. 267-270, 1995.
	10	William J. McCalla, Fundamentals of computer-aided circuit simulation, Kluwer, B.V., Deventer, The Netherlands, 1987
	11	Florentin Dartu , Noel Menezes , Jessica Qian , Lawrence T. Pillage, A gate-delay model for high-speed CMOS circuits, Proceedings of the 31st annual conference on Design automation, p.576-580, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196562]
	12	J. Qian, S. pullela, L.T. Pillage, "Modeling the 'effective capacitance' of the RC interconnect," IEEE Transactions on CAD, vol. 13, pp. 1526-1535, December 1994.
	13	ER O'Brian, T.L. Savarino, "Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation," Proc. IEEE Intl. Conference Computer-Aided Design, pp. 512-515, 1989.
	14	S.A. Kuhn, M.B. Kleiner, E Ramm, W. Weber "Interconnect Capacitances, Crosstalk, and Signal Delay in Vertical Integrated Circuits," Intl. Electronic Device Meeting, pp. 249- 252, 1995.

CITED BY 48

	Paul D. Gross , Ravishankar Arunachalam , Karthik Rajagopal , Lawrence T. Pileggi, Determination of worst-case aggressor alignment for delay calculation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.212-219, November 08-12, 1998, San Jose, California, United States
	Kenneth L. Shepard, Design methodologies for noise in digital integrated circuits, Proceedings of the 35th annual conference on Design automation, p.94-99, June 15-19, 1998, San Francisco, California, United States
	Kanak Agarwal , Yu Cao , Takashi Sato , Dennis Sylvester , Chenming Hu, Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.77, January 07-11, 2002
	Ravishankar Arunachalam , Karthik Rajagopal , Lawrence T. Pileggi, TACO: timing analysis with coupling, Proceedings of the 37th conference on Design automation, p.266-269, June 05-09, 2000, Los Angeles, California, United States
	I. Keller , Ken Tseng , N. Verghese, A robust cell-level crosstalk delay change analysis, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.147-154, November 07-11, 2004
	Masanori Hashimoto , Yuji Yamada , Hidetoshi Onodera, Capturing crosstalk-induced waveform for accurate static timing analysis, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Mattias Ringe , Thomas Lindenkreuz , Erich Barke, Static timing analysis taking crosstallk into account, Proceedings of the conference on Design, automation and test in Europe, p.451-457, March 27-30, 2000, Paris, France
	Richard Trihy, Addressing library creation challenges from recent Liberty extensions, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Lawrence Pileggi, Timing metrics for physical design of deep submicron technologies, Proceedings of the 1998 international symposium on Physical design, p.28-33, April 06-08, 1998, Monterey, California, United States
	Soha Hassoun, Critical path analysis using a dynamically bounded delay model, Proceedings of the 37th conference on Design automation, p.260-265, June 05-09, 2000, Los Angeles, California, United States
	R. Saleh , D. Overhauser , S. Taylor, Full-chip verification of UDSM designs, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.453-460, November 08-12, 1998, San Jose, California, United States
	D. Deschacht , G. Servel, On-chip interconnections: impact of adjacent lines on timing, Proceedings of the 2001 conference on Asia South Pacific design automation, p.539-544, January 2001, Yokohama, Japan
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Reduction of coupling effects by optimizing the 3-D configuration of the routing grid, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.951-954, October 2003
	Supamas Sirichotiyakul , David Blaauw , Chanhee Oh , Rafi Levy , Vladimir Zolotov , Jingyan Zuo, Driver modeling and alignment for worst-case delay noise, Proceedings of the 38th conference on Design automation, p.720-725, June 2001, Las Vegas, Nevada, United States
	Lauren Hui Chen , Malgorzata Marek-Sadowska, Aggressor alignment for worst-case coupling noise, Proceedings of the 2000 international symposium on Physical design, p.48-54, May 2000, San Diego, California, United States
	Vladimir Zolotov , David Blaauw , Rajendran Panda , Chanhee Oh, Cross-Coupled Noise Propagation in VLSI Designs, Analog Integrated Circuits and Signal Processing, v.35 n.2-3, p.133-142, May-June 2003
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Sung-Mo Kang, Minimum delay optimization for domino logic circuits---a coupling-aware approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.203-213, April 2003
	Muzhou Shao , Martin D. F. Wong , Huijing Cao , Youxin Gao , Li-Pen Yuan , Li-Da Huang , Seokjin Lee, Explicit gate delay model for timing evaluation, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Pinhong Chen , Desmond A. Kirkpatrick , Kurt Keutzer, Miller factor for gate-level coupling delay calculation, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Bernard N. Sheehan, Osculating Thevenin model for predicting delay and slew of capacitively characterized cells, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Hiroshi Kawaguchi , Danardono Dwi Antono , Takayasu Sakurai, Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.12, p.2669-2681, December 2007
	Blaise Gassend , Dwaine Clarke , Marten van Dijk , Srinivas Devadas, Delay-based circuit authentication and applications, Proceedings of the 2003 ACM symposium on Applied computing, March 09-12, 2003, Melbourne, Florida
	Tao Lin , Lawrence T. Pileggi, RC(L) interconnect sizing with second order considerations via posynomial programming, Proceedings of the 2001 international symposium on Physical design, p.16-21, April 01-04, 2001, Sonoma, California, United States
	Hai Zhou , Narendra Shenoy , William Nicholls, Timing analysis with crosstalk as fixpoints on complete lattice, Proceedings of the 38th conference on Design automation, p.714-719, June 2001, Las Vegas, Nevada, United States
	Chuan Lin , Hai Zhou, Trade-off between latch and flop for min-period sequential circuit designs with crosstalk, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.329-334, November 06-10, 2005, San Jose, CA
	Cristiano Forzan , Davide Pandini, Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis, Proceedings of the conference on Design, Automation and Test in Europe, p.982-983, March 07-11, 2005
	Bernard N. Sheehan, Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments, Proceedings of the 37th conference on Design automation, p.532-535, June 05-09, 2000, Los Angeles, California, United States
	Bernard N. Sheehan, Predicting coupled noise in RC circuits, Proceedings of the conference on Design, automation and test in Europe, p.517-521, March 27-30, 2000, Paris, France
	Cristiano Forzan , Davide Pandini, A complete methodology for an accurate static noise analysis, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Bhavana Thudi , David Blaauw, Non-iterative switching window computation for delay-noise, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Blaise Gassend , Dwaine Clarke , Marten van Dijk , Srinivas Devadas, Silicon physical random functions, Proceedings of the 9th ACM conference on Computer and communications security, November 18-22, 2002, Washington, DC, USA
	Ki-Wook Kim , Seong-Ook Jung , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, Proceedings of the 38th conference on Design automation, p.732-737, June 2001, Las Vegas, Nevada, United States
	Leonard Lee , Li-C. Wang, On bounding the delay of a critical path, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Seung Hoon Choi , Kaushik Roy , Florentin Dartu, Timed pattern generation for noise-on-delay calculation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware interconnect power optimization in domino logic synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.79-89, February 2003
	Noel Menezes , Chandramouli Kashyap , Chirayu Amin, A "true" electrical cell model for timing, noise, and power grid verification, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Hedi Harizi , Robert Häußler , Markus Olbrich , Erich Barke, Efficient modeling techniques for dynamic voltage drop analysis, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	D. Sinha , Hai Zhou, A unified framework for statistical timing analysis with coupling and multiple input switching, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.837-843, November 06-10, 2005, San Jose, CA
	Chandramouli Kashyap , Chirayu Amin , Noel Menezes , Eli Chiprout, A nonlinear cell macromodel for digital applications, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.203-211, November 08-12, 1998, San Jose, California, United States
	Mattan Kamon , Steve McCormick , Ken Sheperd, Interconnect parasitic extraction in the digital IC design methodology, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.223-231, November 07-11, 1999, San Jose, California, United States
	Bhavana Thudi , David Blaauw, Efficient switching window computation for cross-talk noise, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Mridul Agarwal , Kanak Agarwal , Dennis Sylvester , David Blaauw, Statistical modeling of cross-coupling effects in VLSI interconnects, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Joon-Seo Yim , Seong-Ok Bae , Chong-Min Kyung, A floorplan-based planning methodology for power and clock distribution in ASICs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.766-771, June 21-25, 1999, New Orleans, Louisiana, United States
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Soroush Abbaspour , Massoud Pedram, Gate delay calculation considering the crosstalk capacitances, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.852-857, January 27-30, 2004, Yokohama, Japan
	David Blaauw , Supamas Sirichotiyakul , Chanhee Oh, Driver modeling and alignment for worst-case delay noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.157-166, April 2003