Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.426-436, Dec. 1994  [doi>10.1109/92.335011]
	2	A.bdellatif Bellaouar , Mohamed I. Elmasry , Jonathan Allen, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academic Publishers, Norwell, MA, 1995
	3	X. Hu, S. Bass and R. Harber, "Minimizing the number of delay buffers in the synchronization of pipelined systems", IEEE Trans. on CAD of Integ. Cir. ft Sys, 13(12), 1441-1449, 1994
	4	Xiabo (Sharon) Hu , Garrison W. Greenwood , Joseph G. D'Ambrosio, An Evolutionary Approach to Hardware/ Software Partitioning, Proceedings of the 4th International Conference on Parallel Problem Solving from Nature, p.900-909, September 22-26, 1996
	5	Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak, Optimizing systems for effective block-processing: the k-delay problem, Proceedings of the 33rd annual conference on Design automation, p.714-719, June 03-07, 1996, Las Vegas, Nevada, United States  [doi>10.1145/240518.240653]
	6	C. Leiserson and J. Saxe, "Retiming synchronous circuitry', Algorithmiea, 6(1), 5-35, 1991
	7	José Monteiro , Srinivas Devadas , Pranav Ashar , Ashutosh Mauskar, Scheduling techniques to enable power management, Proceedings of the 33rd annual conference on Design automation, p.349-352, June 03-07, 1996, Las Vegas, Nevada, United States  [doi>10.1145/240518.240584]
	8	M. Potkonjak and J. Rabaey, "Pipelining: just another transformation", Int'l Conf. on Application Specific Array Processors, 163-175, 1992
	9	Massoud Pedram , Jan M. Rabaey, Power Aware Design Methodologies, Kluwer Academic Publishers, Norwell, MA, 2002
	10	Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States  [doi>10.1145/224081.224120]

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