High-performance, low-power design techniques for dynamic to static logic interface

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High-performance, low-power design techniques for dynamic to static logic interface

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 12 - 17

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

June Jiang	Texas Instruments Incorporated, P.O. Box 660199, M/S 8723, Dallas, Texas
Kan Lu	Texas Instruments Incorporated, P.O. Box 660199, M/S 8723, Dallas, Texas
Uming Ko	Texas Instruments Incorporated, P.O. Box 660199, M/S 8723, Dallas, Texas

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 0

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references collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R.H. Krambeck. C. M. Lee and H. E S. Law, "High-speed compact circuits with CMOS,' IEEE J. Solid State Circuits, vol. 17. no. 3, pp. 614-619, June 1982.
	2	P. Larsson and C. Svensson, "Noise in Digital Dynamic CMOS Circuits,' IEEE J. of Solid State Circuits, vol. 29. no. 6, pp. 655-662, JUNE 1994.
	3	E.T. Lewis, "An analysis of interconnect line capacitance and coupling for VLSI circuits,' Solid-State Electron., vol. 27. nos.8-9, pp. 741-749, 1984
	4	William J. Bowhill , Shane L. Bell , Bradley J. Benschneider , Andrew J. Black , Sharon M. Britton , Ruben W. Castelino , Dale R. Donchin , John H. Edmondson , Harry R. Fair , Paul E. Gronowski , Anil K. Jain , Patricia L. Kroesen , Marc E. Lamere , Bruce J. Loughlin , Shekhar Mehata , Sribalan Santhanam , Timothy A. Shedd , Stephen C. Thierauf , Robert O. Mueller , Ronald P. Preston , Michael J. Smith, Circuit implementation of a 300-MHz 64-bit second-generation CMOS Alpha CPU, Digital Technical Journal, v.7 n.1, p.100-118, Jan. 1995
	5	G. A. Katopis. "Delta-I noise specification for a highperformance computing machine," Proc. of the IEEE. vol. 73. no.9, pp. 1405-1415, Sept. 1985
	6	J. Yuan, I. Karlsson, and C. Svensson, "Hew Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings" IEEE J. of Solid State Circuits, vol. 32, no. 1, pp. 62-67, Jan. 1997.
	7	J. M. Zurada, Y. S. Joo and S. V. Bell, "Dynamic noise margin of MOS logic gates,' Proc. of ISCAS'89, vol. 2, pp. 1153-1156, May 1989

Collaborative Colleagues:

June Jiang: colleagues

Kan Lu: colleagues

Uming Ko: colleagues

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