Sequential logic optimization by redundancy addition and removal

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Sequential logic optimization by redundancy addition and removal

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 310 - 315

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Luis Entrena	Universidad Politecnica de Madrid, ETSII-DIE, Jose Gutierrez Abascal, 228006 Madrid, Spain
Kwang-Ting Cheng	AT&T Bell Laboratories, Murray Hill, NJ

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 37, Citation Count: 40

Additional Information:

references cited by collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K.-T. Cheng and Luis A. Entrena, "Multi-Level Logic Optimization by Redundancy Addition and Removal," European Conf. on Design Automation (EDAC-93) (Feb. 1993).
	2	D. Bostick et al, "The Boulder Optimal LogJLc Design System ," Proc. Int'l Conf. CAD, pp. 62-65 (Nov. 1987).
	3	S. MaRk, E. M. Sentovieh, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Teclniques," IEEE Trans. on CAD 10(1), pp. "/4-84 (J'anuaJry 1991).
	4	Y. Matsunaga, M. Fujita, and T. Kakuda, "Multi-level Logic Minimization Across Latch Boundaries," Proc. In,r,'l Conf. CAD, pp. 406-409 (November 1990).
	5	Kwang-Ting Cheng, On removing redundancy in sequential circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.164-169, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127655]
	6	Hyunwoo Cho , Gary D. Hachtel , Fabio Somenzi, Redundancy Identification and Removal Based on Implicit State Enumeration, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.77-80, October 14-16, 1991
	7	Wolfgang Kunz , Dhiraj K. Pradhan, Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.816-825, September 20-24, 1992
	8	T. Kirkland , M. R. Mercer, A topological search algorithm for ATPG, Proceedings of the 24th ACM/IEEE conference on Design automation, p.502-508, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37963]
	9	M. Schulz and El Auth, "Advanced Automatic Test Patt~;m Generation and Redundancy Identification Techniques," Proc. Fault Tolerant Computing Symposium, pp. 30-35 (June 1988).
	10	P. Muth, "A Nine-Valued Circuit Model for Test Generation," IEEE Trans. Computers C-25, pp. 630-636 (June 1976).
	11	R.K. Brayton, R. RudeU, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: Multi-level Interactive Logic Optimization System," IEEE Trans. on CAD CAD-6(6), pp. 1062-1081 (Nov. 1989).
	12	H. Savoj, H.-Y. Wang, and R. K. Brayton, "Improved Scripts in MIS-II for Logic Minimization of Combinational Circuits," Int't Workshop in Logic Synthesis (April 1990).

CITED BY 40

	J. Espejo , L. Entrena , E. San Millán , E. Olias, Generalized reasoning scheme for redundancy addition and removal logic optimization, Proceedings of the conference on Design, automation and test in Europe, p.391-397, March 2001, Munich, Germany
	J. A. Espejo , L. Entrena , E. San Millán , E. Oliás, Functional extension of structural logic optimization techniques, Proceedings of the 2001 conference on Asia South Pacific design automation, p.467-472, January 2001, Yokohama, Japan
	M. Henftling , H. C. Wittmann , K. J. Antreich, A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.304-309, November 05-09, 1995, San Jose, California, United States
	Ki-Wook Kim , C. L. Liu , Sung-Mo Kang, Implication graph based domino logic synthesis, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.111-114, November 07-11, 1999, San Jose, California, United States
	Chin-Ngai Sze , Yu-Liang Wu, Improved alternative wiring scheme applying dominator relationship, Proceedings of the 2001 conference on Asia South Pacific design automation, p.473-478, January 2001, Yokohama, Japan
	Irith Pomeranz , Sudhakar M. Reddy, Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.679-689, October 2001
	Slawomir Pilarski , Gracia Hu, SAT with partial clauses and back-leaps, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	L. Entrena , E. Olías , J. Uceda , J. Espejo, Timing optimization by an improved redundancy addition and removal technique, Proceedings of the conference on European design automation, p.342-347, September 1996, Geneva, Switzerland
	Shih-Chieh Chang , Kwang-Ting Cheng , Nam-Sung Woo , Malgorzata Marek-Sadowska, Layout driven logic synthesis for FPGAs, Proceedings of the 31st annual conference on Design automation, p.308-313, June 06-10, 1994, San Diego, California, United States
	Q. Wang , S. B. K. Vrudhula, Data driven power optimization of sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.686-691, February 23-26, 1998, Le Palais des Congrés de Paris, France
	R. Mukherjee , J. Jain , M. Fujita, VERIFUL: VERIfication using FUnctional Learning, Proceedings of the 1995 European conference on Design and Test, p.444, March 06-09, 1995
	Qi Wang , Sarma B. K. Vrudhula, Multi-level logic optimization for low power using local logic transformations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.270-277, November 10-14, 1996, San Jose, California, United States
	S.-C. Chang , D. I. Cheng , C.-W. Yeh, On removing multiple redundancies in combinational circuits, Proceedings of the conference on Design, automation and test in Europe, p.738-742, February 23-26, 1998, Le Palais des Congrés de Paris, France
	R. Bahar , M. Burns , G. Hachtel , E. Macii , H. Shin , F. Somenzi, Symbolic computation of logic implications for technology-dependent low-power synthesis, Proceedings of the 1996 international symposium on Low power electronics and design, p.163-168, August 12-14, 1996, Monterey, California, United States
	Jawahar Jain , Rajarshi Mukherjee , Masahiro Fujita, Advanced verification techniques based on learning, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.420-426, June 12-16, 1995, San Francisco, California, United States
	Qi Wang , Sarma B. K. Vrudhula , Gary Yeap , Shantanu Ganguly, Power reduction and power-delay trade-offs using logic transformations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.1, p.97-121, Jan. 1999
	Shih-Chieh Chang , Malgorzata Marek-Sadowska, Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares, Proceedings of the 1996 European conference on Design and Test, p.402, March 11-14, 1996
	Shih-Chieh Chang , Malgorzata Marek-Sadowska , Kwang-Ting Cheng, An efficient algorithm for local don't care sets calculation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.663-667, June 12-16, 1995, San Francisco, California, United States
	A. Mehrotra , S. Qadeer , V. Singhal , R. K. Brayton , A. Aziz , A. L. Sangiovanni-Vincentelli, Sequential optimisation without state space exploration, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.208-215, November 09-13, 1997, San Jose, California, United States
	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Fast Boolean optimization by rewiring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.262-269, November 10-14, 1996, San Jose, California, United States
	Vigyan Singhal , Carl Pixley , Adnan Aziz , Robert K. Brayton, Exploiting power-up delay for sequential optimization, Proceedings of the conference on European design automation, p.54-59, September 18-22, 1995, Brighton, England
	Shih-Chieh Chang , Malgorzata Marek-Sadowska, Perturb and simplify: multi-level boolean network optimizer, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.2-5, November 06-10, 1994, San Jose, California, United States
	Vigyan Singhal , Carl Pixley , Adnan Aziz , Shaz Qadeer , Robert Brayton, Sequential optimization in the absence of global reset, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.222-251, April 2003
	Carl Pixley , Vigyan Singhal , Adnan Aziz , Robert K. Brayton, Multi-level synthesis for safe replaceability, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.442-449, November 06-10, 1994, San Jose, California, United States
	Wolfgang Kunz , Prem R. Menon, Multi-level logic optimization by implication analysis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.6-13, November 06-10, 1994, San Jose, California, United States
	Subarnarekha Sinha , Andreas Kuehlmann , Robert K. Brayton, Sequential SPFDs, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Circuit Optimization by Rewiring, IEEE Transactions on Computers, v.48 n.9, p.962-970, September 1999
	Mahesh A. Iyer , David E. Long , Miron Abramovici, Surprises in Sequential Redundancy Identification, Proceedings of the 1996 European conference on Design and Test, p.88, March 11-14, 1996
	Irith Pomeranz , Sudhakar M. Reddy, On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences, IEEE Transactions on Computers, v.45 n.1, p.20-32, January 1996
	Catherine L. Zhou , Wai-Chung Tang , Wing-Hang Lo , Yu-Liang Wu, How much can logic perturbation help from netlist to final routing for FPGAs, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	Huey-Yih Wang , Robert K. Brayton, Multi-level logic optimization of FSM networks, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.728-735, November 05-09, 1995, San Jose, California, United States
	Mahesh A. Iyer , David E. Long , Miron Abramovici, Identifying sequential redundancies without search, Proceedings of the 33rd annual conference on Design automation, p.457-462, June 03-07, 1996, Las Vegas, Nevada, United States
	João P. Marques-Silva , Karem A. Sakallah, Boolean satisfiability in electronic design automation, Proceedings of the 37th conference on Design automation, p.675-680, June 05-09, 2000, Los Angeles, California, United States
	Chih-chang Lin , Malgorzata Marek-Sadowska , Kuang-Chien Chen , Mike Tien-Chien Lee, Sequential Permissible Functions and their Application to Circuit Optimization, Proceedings of the 1996 European conference on Design and Test, p.334, March 11-14, 1996
	Fabrizio Ferrandi , Franco Fummi , Enrico Macii , Massimo Poncino , Donatella Sciuto, Symbolic optimization of FSM networks based on sequential ATPG techniques, Proceedings of the 33rd annual conference on Design automation, p.467-470, June 03-07, 1996, Las Vegas, Nevada, United States
	W. B. Jone , Y. P. Ho , S. R. Das, Delay Fault Coverage Enhancement Using Variable Observation Times, Journal of Electronic Testing: Theory and Applications, v.11 n.2, p.131-146, Oct. 1997
	Irith Pomeranz , Sudhakar M. Reddy, On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.2, p.175-182, February 2000
	Yu-Liang Wu , Chak-Chung Cheung , David Ihsin Cheng , Hongbing Fan, Further improve circuit partitioning using GBAW logic perturbation techniques, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.451-460, June 2003
	Yu-Liang Wu , Chak-Chung Cheung , David Ihsin Cheng , Hongbing Fan, Further improve circuit partitioning using GBAW logic perturbation techniques, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.451-460, June 2003

Collaborative Colleagues:

Luis Entrena: colleagues

Kwang-Ting Cheng: colleagues

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