On-chip test generation for combinational circuits by LFSR modification

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

On-chip test generation for combinational circuits by LFSR modification

Full text

Pdf (466 KB)

Source

International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 84 - 87

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Shambhu J. Upadhyaya	Dept. of Electrical and Computer Engineering, State University of New York at Buffalo, Buffalo, New York
Liang-Chi Chen	Dept. of Electrical and Computer Engineering, State University of New York at Buffalo, Buffalo, New York

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 3

Additional Information:

references cited by collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
	2	J. Savir, G. Ditlow, and P. Bardell, "Random pattern testability," IEEE Trans. Computers, vol. C- 33, no. 1, pp. 79-90, 1984.
	3	B. Koenemann, J. Mucha, and G. Zwiehoff, "Built-in logic block observation," Dig. 1979 Test Conf., pp. 37-41, 1979.
	4	F. Siavoshi, "WTPGA: A novel weighted test pattern generation approach for VLSI built-in self test," 1EEE Int. Test Conf., pp. 256-I!62, 1988.
	5	J. Waicukauski and E. Lindbloom, "Fault detection effectiveness of weighted random patterns," 1EEE Int. Test Conf., pp. 245-255, 1988.
	6	J. Savir , H. McAnney, A multiple seed linear feedback shift register, IEEE Transactions on Computers, v.41 n.2, p.252-256, February 1992 [doi>10.1109/12.123405]
	7	W. Daehn and J. Mucha, "A hardware approach to self testing of large PLAs," IEEE Trans. Computers, vol. C-30, no. 11, pp. 829-833, 1981.
	8	R. Raina and P. Marinos, "Signature analysis with modified LFSRs," FTCS-21, pp. 88-95, '91.
	9	Sybille Hellebrand , Steffen Tarnick , Bernard Courtois , Janusz Rajski, Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.120-129, September 20-24, 1992
	10	F. Muradali, V. Agarwal, and B. Dostie, "A new procedure for weighted random built-in self-test," 1EEE Int. Test Conf., pp. 660-669, 1990.
	11	F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proc. 1EEE Int. Symp. Circuits and Systems, pp. 663-698, 1985.
	12	Hyung Ki Lee , Dong Sam Ha, SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits, Proceedings of the 27th ACM/IEEE conference on Design automation, p.660-666, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123432]
	13	J. Savir, "Private communication," Jan. 1993.
	14	C. Lin and S. Reddy, "On delay fault testing in logic circuits," 1EEE Trans. on CAD, vol. CAD- 6, no. 5, pp. 694-703, Sept. 1987.

CITED BY 3

	Li-Ren Huang , Sy-Yen Kuo , Ing-Yi Chen, A Gauss-elimination based PRPG for combinational circuits, Proceedings of the 1995 European conference on Design and Test, p.212, March 06-09, 1995
	Irith Pomeranz , Sudhakar M. Reddy, A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set, IEEE Transactions on Computers, v.51 n.11, p.1282-1293, November 2002
	Mitrajit Chatterjee , Dhiraj K. Pradhan, A BIST Pattern Generator Design for Near-Perfect Fault Coverage, IEEE Transactions on Computers, v.52 n.12, p.1543-1558, December 2003

Collaborative Colleagues:

Shambhu J. Upadhyaya: colleagues

Liang-Chi Chen: colleagues

Peer to Peer - Readers of this Article have also read:

LR Parsing ACM Computing Surveys (CSUR) 6, 2
A. V. Aho , S. C. Johnson

Adobe Acrobat

QuickTime

Windows Media Player

Real Player