Performance driven floorplanning for FPGA based designs

ABSTRACT

Increasing design densities on large FPGAs and greater demand for performance, has calledfor special purpose tools like floorplanner, performance driven router, and more. In this paper we present a floorplanning based design mapping solution that is capable of mapping macro cell based designs as well as hierarchicaldesigns on FPGAs. The mapping solution has been tested extensively on a large collection of designs. We not only outperform state of the art CAE tools from industry in terms of execution time but also achieve much better performance in terms of timing. These methods are especially suitable for mapping designs on very large FPGAs.

REFERENCES

• 1: H. Kitazawa K. Ueda and I. Harada. CHAPM: Chip floorplan for hierarchical VLSI layout. IEEE Transaction on Computer Aided Design, 4(1):12-22,1985.
• 2: Ravi Nair, C.Leonard Berman, Peter S. Hauge, and Ellen J.Yoffa. Generation of Performance Constraints for Layout. IEEE Transactions on Computer Aided Design, 8(8):860-874, August 1989.
• 3: Ralph H.J.M. Otten, Automatic floorplan design, Proceedings of the 19th conference on Design automation, p.261-267, January 1982
• 4: S. Prasitjutrakul , W. J. Kubitz, Path-delay constrained floorplanning: a mathematical programming approach for initial placement, Proceedings of the 26th ACM/IEEE conference on Design automation, p.364-369, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74443]
• 5: S. Sastry and A. Parker. The complexity of the twodimensional compaction of ~LSI layout, in Proc. Intl Conference Circuit and Computer, pages 402--406, September 1982.
• 6: Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, Norwell, MA, 1993
• 7: Larry Stockmeyer, Optimal orientations of cells in slicing floorplan designs, Information and Control, v.57 n.2-3, p.91-101, May/June 1983 [doi>10.1016/S0019-9958(83)80038-2]
• 8: Suphachai Sutanthavibul , Eugene Shragowitz , J. Ben Rosen, An analytical approach to floorplan design and optimization, Proceedings of the 27th ACM/IEEE conference on Design automation, p.187-192, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123255]
• 9: D.F. Wong T. Mueller and C.L. Liu. An Enhanced Bottom-up Algorithm for Floorplan Design. Proc. of the ~Jth A CM/IEEE Design Automation Conference, pages 524-527, 1987.
• 10: G. Vijayan and R. Tsay. A new method for floorplanningusing topological constraint reduction. IEEE Transaction on CAD, 10(12):1494-1501, December 1991.
• 11: D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States
• 12: XinrLx, Inc., San Sose, Canfornia. Floo~pl~er nefe,~nce/User Guide, 1995.
• 13: Habib Youssef , Sadiq M. Sait , Khalid J. Al-Farra, Timing influenced force directed floorplanning, Proceedings of the conference on European design automation, p.156-161, September 18-22, 1995, Brighton, England

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Algorithms, Design, Performance