ACM Home Page
Please provide us with feedback. Feedback
Improving functional density through run-time constant propagation
Full text PdfPdf (1,000 KB)
Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays table of contents
Monterey, California, United States
Pages 86-92  
Year of Publication: 1997
ISBN:0-89791-801-0
Authors
Michael J. Wirthlin  Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT
Brad L. Hutchings  Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 17,   Citation Count: 8
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/258305.258316
What is a DOI?

ABSTRACT

Circuit specialization techniques such as constant propagation are commonly used to reduce both the hardware resources and cycle time of digital circuits. When reconfigurable FPGAs are used, these advantages can be extended by dynamically specializing circuits using run-time reconfiguration (RTR). For systems exploiting constant propagation, hardware resources can be reduced by folding constants within the circuit and dynamically changing the constants using circuit reconfiguration. To measure the benefits of circuit specialization, a functional density metric is presented. This metric allows the analysis of both static and run-time reconfigured circuits by including the cost of circuit reconfiguration. This metric will be used to justify runtime constant propagation as well as analyze the effects of reconfiguration time on run-time reconfigured systems.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
P. W. Foulk. Data-folding in SRAM configurable FPGAs. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 163-171, Napa, CA, April 1993.
 
2
 
3
A. Girl, V. Visvanathan, S.K. Nandy, and S.K. Ghoshal. High speed digital filtering on SRAM- based FPGAs. 7th International Conference on VLSI Design, pages 229-232, January 1994.
 
4
 
5
G. It. Goslin. Using Xilinx FPGAs to design custom digital signal processing devices. In 1995 Proceedings of DSPX, pages 565-604, January 1995.
 
6
C. Chou, S. Mohanakrishnan, and j. B. Evans. FPGA implementation of digital filters. In Proceedings of the Fourth International Conference on Signal Processing Applications and Technology, pages 80-88, Santa Clara, CA, 1993.
 
7
M. van Daalen, P. Jeavons, and J. Shawe-Taylor. A stochastic neural architecture that exploits dynamically reconfigurable FPGAs. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 202-211, Napa, CA, April 1993.
 
8
C.E. Cox and W. E. Blanz. GANGLION - a fast field-programmable gate array implementation of a connectionist classifier. IEEE Journal of Solid- State Circuits, 27(3):288-299, March 1992.
 
9
B. Gunther, G. Milne, and L. Narasimhan. Assessing document relevance with run-time reconfigurable machines. In J. Arnold and K. L. Pocek, editors, Proceedings of iEEE Workshop on FP- GAs for Custom Computing Machines, Napa, CA, April 1996.
 
10
 
11
 
12
 
13
J. Villasenor, B. Schoner, K. Chia, and C. Zapata. Configurable computing solutions for automatic target recognition. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, April 1996.
 
14
Michael A. Rencher. A comparison of FPGA platforms through SAR/ATR algorithm implementation. Master's thesis, Brigham Young University, 1996.
 
15
National Semiconductor. Configurable Logic Array (CLAy) Data Sheet, December 1993.
 
16
Atmel, San Jose, CA. Configurable Logic: Design F.4 Application Book, 1993-1994.
 
17
Xilinx. XC6~00 Field Programmable Gate Arrays, 1996.
 
18

CITED BY  8
 
 
 
 
 

Collaborative Colleagues:
Michael J. Wirthlin: colleagues
Brad L. Hutchings: colleagues

Peer to Peer - Readers of this Article have also read: