The Transmogrifier-2: a 1 million gate rapid prototyping system

ABSTRACT

This paper describes the Transmogrifier-2, a second generation multi-FPGA system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGAs, four I-cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a non-uniform partial crossbar, that provides a constant delay between any two FPGAs in the system. The TM-2 architecture is modular and scalable, meaning that various sized systems can be constructed from the same board, while maintaining routability and the constant delay feature. Other features include a system-level programmable clock that allows single-cycle access to off-chip memory, and programmable clock waveforms with resolution to 10ns. The first Transmogrifier-2 boards have been manufactured and are functional. They have recently been used successfully in some simple graphics acceleration applications.

REFERENCES

• 1: Michael Butts , Jon Batcheller , Joseph Varghese, An Efficient Logic Emulation System, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.138-141, October 11-14, 1992
• 2: M. Slimane-Kadi, D. Brasen, G. Saucier, ".4, Fast-FPGA Prototyping System That Uses Inexpensive High-Performance FPiC", in Proc. 2nd Annual Workshop on FPGAs, 1994
• 3: R. Tessier, J. Babb, M. Dashl, S. Hanon, A. Agarwal, "The Virtual Wires Emulation System: A Gate-Efficient ASIC Prototyping Environment", Proc.2nd Annual Workshop on FPGAs, 1994
• 4: J. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, P. Boucard, "Programmable Active Memories: Reconfigurable Systems Come of Age", Proc. IEEE Trans VLSI Systems, March 1996, pp. 56-69
• 5: Jeffrey M. Arnold , Duncan A. Buell , Elaine G. Davis, Splash 2, Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures, p.316-322, June 29-July 01, 1992, San Diego, California, United States [doi>10.1145/140901.141896]
• 6: R. Amerson , R. J. Carter , W. B. Culbertson , P. Kuekes , G. Snider, Teramac-configurable custom computing, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.32, April 19-21, 1995
• 7: D. Galloway, D. Karchmer, D. Chow, D. Lewis, J. Rose, "The Transmogrifier: The University of Toronto Field- Programmable System", Second Canadian Workshop on Field-Programmable Devices, Kingston, Ontario, June 1994. Also available as CSRI Technical Report 306 via anonymous ftp from ftp:llftp.csri.toronto.edulcsri-technical-reports!3061.
• 8: P. Chart and M. Schlag, "Architectural Tradeoffs in Programmable-device-Based Computing Systems", in Proc. FPGAs for Custom Computing Machines, 1993, pp 152-161
• 9: D. Galloway, The Transmogrifier C hardware description language and compiler for FPGAs, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.136, April 19-21, 1995
• 10: M. Khalid and J. Rose, "The Effect of Fixed I/O Hn Positioning on The Routability and Speed of FPGAs," Proc. Canadian Workshop of Field-Programmable Devices, FPD 95, pp. 94-102.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Placement and routing

General Terms:
Algorithms, Design