I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning

ABSTRACT

We improve upon a new approach for automatically partitioning a system among several FPGAs. The new approach partitions a system's functional specification, now commonly available, rather than its structural implementation. The improvement uses a bus, the FunctionBus, for implementing function calls among FPGA's, The bus can be used with any number of and its protocol uses only a small amount of existing FPGA hardware, requiring no special hardware. While functional rather than structural partitioning can substantially reduce the number of input/output pins using (I/O) the FunctionBus takes such reduction even further. In particular, performance and I/0can be traded-off by varying the bus size, as demonstrated using several examples.

REFERENCES

• 1: Charles J. Alpert , Andrew B. Kahng, Recent directions in netlist partitioning: a survey, Integration, the VLSI Journal, v.19 n.1-2, p.1-81, Aug. 1995 [doi>10.1016/0167-9260(95)00008-4]
• 2: D. Brasen and G. Saucier, "FPGA partitioning for critical paths," in Proceedings of the European Design and Test Conference (EDTC), pp. 99-103, 1994.
• 3: Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral-based multi-way FPGA partitioning, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.133-139, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201331]
• 4: N. Chou, L. Liu, C. Cheng, W. Dai, and R. Lindelof, "Local ratio cut and set covering partitioning for huge logic emulation systems," in IEEE Transactions on Computer-Aided Design, pp. 1085-1092, 1995.
• 5: Scott Hauck , Gaetano Borriello, Logic partition orderings for multi-FPGA systems, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.32-38, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201315]
• 6: Dennis J.-H. Huang , Andrew B. Kahng, Multi-way system partitioning into a single type or multiple types of FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.140-145, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201332]
• 7: Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
• 8: Kalapi Roy-Neogi , Carl Sechen, Multiple FPGA partitioning with performance optimization, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.146-152, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201333]
• 9: Prashant Sawkar , Donald Thomas, Multi-way partitioning for minimum delay for look-up table based FPGAs, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.201-210, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217530]
• 10: R. Tessier, J. Babb, M. Dahl, S. Hanono, and A. Agarwal, "The virtual wires emulation system: A gate-efficient asic prototyping environment," in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPCA), X004.
• 11: Frank M. Johannes, Partitioning of VLSI circuits and systems, Proceedings of the 33rd annual conference on Design automation, p.83-87, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240535]
• 12: Vahid , Le , Hsu, A Comparison of Functional and Structural Partitioning, Proceedings of the 9th international symposium on System synthesis, p.121, November 06-08, 1996
• 13: E. Lagnese and D. Thomas, "Architectural partitioning for system level synthesis of integrated circuits," IEEE Transactions on Computer-Aided Design, vol. 10, pp. 847-860, July 1991.
• 14: R. Gupta and G. DeMicheli, "Partitioning of functional models of synchronous digital systems," in Proceedings of the International Conference on Computer-Aided Design, pp. 216-219, 1990.
• 15: Kayhan Kükçakar , Alice C. Parker, CHOP: A constraint-driven system-level partitioner, Proceedings of the 28th conference on ACM/IEEE design automation, p.514-519, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127724]
• 16: Y. Chen, Y. Hsu, and C. King, "MULTIPAR: Behavioral partition for synthesizing multiprocessor architectures," IEEE Transactions on Very Large Scale Integration Systems, vol. 2, pp. 21-32, March 1994.
• 17: C. Gebotys, "An optimization approach to the synthesis of multichip architectures," IEEE Transactions on Very Large Scale Integration Systems, vol. 2, no. 1, pp. 11-20, 1994.
• 18: F. Vahid , D. D. Gajski, Specification partitioning for system design, Proceedings of the 29th ACM/IEEE conference on Design automation, p.219-224, June 08-12, 1992, Anaheim, California, United States
• 19: Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470]
• 20: Rolf Ernst , Jorg Henkel , Thomas Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test, v.10 n.4, p.64-75, October 1993 [doi>10.1109/54.245964]
• 21: Daniel D. Gajski , Frank Vahid , Sanjiv Narayan , Jie Gong, Specification and design of embedded systems, Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
• 22: Xun Xiong , Edna Barros , Wolfgang Rosenstiel, A method for partitioning UNITY language in hardware and software, Proceedings of the conference on European design automation, p.220-225, September 19-23, 1994, Grenoble, France
• 23: Asawaree Kalavade , Edward A. Lee, A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem, Proceedings of the 3rd international workshop on Hardware/software co-design, September 22-24, 1994, Grenoble, France
• 24: Petru Eles , Zebo Peng , Alexa Doboli, VHDL system-level specification and partitioning in a hardware/software co-synthesis environment, Proceedings of the 3rd international workshop on Hardware/software co-design, September 22-24, 1994, Grenoble, France
• 25: Peter Voigt Knudsen , Jan Madsen, PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.85, March 18-20, 1996
• 26: A. Balboni , W. Fornaciari , D. Sciuto, Partitioning and Exploration Strategies in the TOSCA Co-Design Flow, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.62, March 18-20, 1996
• 27: Frank Vahid , Daniel D. Gajski, Incremental hardware estimation during hardware/software functional partitioning, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.3, p.459-464, Sept. 1995 [doi>10.1109/92.407006]
• 28: Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
• 29: F. Vahid , D. D. Gajski, SLIF: a specification-level intermediate format for system design, Proceedings of the 1995 European conference on Design and Test, p.185, March 06-09, 1995
• 30: F. Vahid, Procedure cloning: a transformation for improved system-level functional partitioning, Proceedings of the 1997 European conference on Design and Test, p.487, March 17-20, 1997

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

General Terms:
Algorithms, Design, Performance