On the testing of microprogrammed processor

ABSTRACT

In this paper a testing procedure is given for a microprogrammed processor. The conventional procedure to generate test vectors is used instead of C-testability for bit-slice microprocessor. The minimal complete test sequences are calculated for the micro-sequencer and the ALU, and stored in the micro-memory. Micro-memory is implemented by an electrically erasable PLA which has the capability to test itself using a universal test set. A one-bit wide processor section has been assumed in this paper. However, the method can be extended to a processor of any word length. The tests for the microsequencer and the ALU are applied from the micromemory. The response is compared against precalculated signature stored in the system memory. A parity bit is generated to indicate a fault.

REFERENCES

• 1: C. Robach and G. Saucier, "Dynamic Testing of Control Units", IEEE Trans. Comp., vol. c-27(7), pp. 617-623, July 1978.
• 2: C. Robach and G. Saucier, "Microprocessor Functional Testing", Proc. Int. Test Conf., pp. 433-443, 1980.
• 3: K. K. Saluja, Li Shen and S. Y. H. Su, "a Simplified Algorithm for Testing Microprocessors", Proc. Int. Test Conf., pp. 668-675, 1983.
• 4: Stephen Y.H. Su , Tonysheng Lin, Functional testing techniques for digital LSI/VLSI systems, Proceedings of the 21st conference on Design automation, p.517-528, June 25-27, 1984, Albuquerque, New Mexico, United States
• 5: Y. K. Malaiya, On inherent untestability of unaugmented microprogrammed control, Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture, p.88-96, August 14-16, 1989, Dublin, Ireland
• 6: S. M. Thatte and J. A. Abraham, "Test Generation for Microprocessors", IEEE Trans. Comp., vol. c- 29(6), pp. 429-441, June 1980.
• 7: D. Brahme and J. A. Abraham, "Functional Testing of Microprocessors", IEEE Trans. Comp., vol. c- 33(6), pp. 475-485, June, 1984.
• 8: T. Sridhar and J. P. Hayes, "Design of Easily Testable Bit-Sliced Systems", IEEE Trans. Comp., vol. c-30(11), pp. 324-336, Nov. 1981.
• 9: T. Sridhar and J. P. Hayes, "A Functional Approach to Testing Bit-Sliced Microprocessors", IEEE Trans. Comp., vol. c-30(8), pp. 563-571, Aug. 1981.
• 10: R. Rajsuman. "Design of highly testable and fault diagnosable, reprogrammable FPLA", Technical Report, Department of Computer Engineering and Science, Case Western Reserve University, Cleveland, Ohio, 1990.