| PRISM architecture: parallel and pipeline features |
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International Symposium on Microarchitecture
archive
Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
table of contents
Orlando, Florida, United States
Pages: 230 - 236
Year of Publication: 1990
ISBN:0-89791-413-9
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IEEE Computer Society Press
Los Alamitos, CA, USA
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Downloads (6 Weeks): 0, Downloads (12 Months): 11, Citation Count: 0
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ABSTRACT
Reconstruction of Computer Tomography images requires several processing steps for reduction of electronic noise and correction of physical inaccuracies. The most time-consuming step is a convolution implemented with Fast Fourier Transforms. The architecture of a single board computer designed to provide an efficient implementation of the Fast Fourier Transform is presented. Parallel and pipeline features are discussed and a typical array routine is used to present software features.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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C. Brunnett, B. Gocal, M. Kerber, J. Pexa and C. Vrettos, U.S. patent, "PRISM Architecture for CT Image Recontruction", filed Aug., 1989
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C. Brunnett, B. Gocal, M. Kerber, J. Pexa and C. Vrettos, U.S. patent, "An Array Processor with Custom Processor Elements and an Arithmetic Section", filed Nov., 1988
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M. Kerber and J. Sidoti, U.S. patent, "Custom Integrated Circuit to Facilitate High Speed Digital Signal Processing Computations", filed Nov., 1988
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Weitek Specifications, "WTL 2264/WTL 2265 Floating Point Multiplier/Divider and ALU", Weitek Corporation, 1060 E. Arques, Sunnyvale, Calif. 94086, 1987
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Handler, W., "The Impact of Classification Schemes on Computer Architecture", Proc. 1977 International Conference on Parallel Processing, pp 7-15.
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