A multiple floating point coprocessor architecture

ABSTRACT

General purpose microprocessor based computers usually speed their arithmetic processing performance by using a floating point co-processor. Because adding more co-processors represents neither a technological nor a cost problem we investigated a system based on a MIPS R2000 [2] and 4 floating point units. In this paper we show a block diagram of such an implementation and how two important scientific operations can be accelerated using a single unmodified data bus. A large percentage of the engineering applications are solved with the help of linear algebra methods like BLAS3 [4] algorithms; It is precisely for these primitives that the proposed architecture brings significant performance gains. The first operation described will be a matrix multiplication algorithm, its timing diagram and some results, Next a polynomial evaluation technique will be examined. Finally we show how to use the same ideas with various other microprocessors.

REFERENCES

• 1: Weitek Corporation, Weitek WTL 3164/XL-3164 WTL 3364/XL-3364 Data Sheet, Sunnyvale CA, 1988
• 2: Gerry Kane, MIPS RISC architecture, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
• 3: Shlomo Waser , Michael J. Flynn, Introduction to Arithmetic for Digital Systems Designers, Harcourt Brace College Publishers, 1995
• 4: K. Gallivan, W. Jalby, U. Meier and A. Sameh, The Impact of Hierarchical Memory Systems on Linear Algebra Algorithm Design, International Journal of Supercomputing Applications, Vol.2 No 1, Spring 1988