A memory management unit and cache controller for the MARS system

ABSTRACT

For large caches, the interaction between cache access and address translation affects the machine cycle time and the access time to memory. The physically addressed caches slow down the cache access due to the virtual address translation. The virtually addressed caches is faster, but the synonym problem is difficult to handle. By some software constraints and hardware support, our virtually addressed physically tagged caches can achieve the same speed as traditional virtually addressed cache and solve the synonym problem. The design of delayed miss signal makes the TLB access depart from the critical path of the cache access. A simple method to solve the TLB coherence is implemented in this chip and only a little hardware is required.

REFERENCES

• 1: Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
• 2: James R. Goodman, Using cache memory to reduce processor-memory traffic, Proceedings of the 10th annual international symposium on Computer architecture, p.124-131, June 13-17, 1983, Stockholm, Sweden
• 3: S. Prybylski , M. Horowitz , J. Hennessy, Performance tradeoffs in cache design, Proceedings of the 15th Annual International Symposium on Computer architecture, p.290-298, May 30-June 02, 1988, Honolulu, Hawaii, United States
• 4: J. H. Chang , H. Chao , K. So, Cache design of a sub-micron CMOS system/370, Proceedings of the 14th annual international symposium on Computer architecture, p.208-213, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30374]
• 5: Kai Hwang , Faye A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, Inc., New York, NY, 1990
• 6: D. A. Wood , S. J. Eggers , G. Gibson , M. D. Hill , J. M. Pendleton, An in-cache address translation mechanism, Proceedings of the 13th annual international symposium on Computer architecture, p.358-365, June 02-05, 1986, Tokyo, Japan
• 7: L. M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, Vol. C-27, No.12, December 1978.
• 8: D. R. Cheriton , G. A. Slavenburg , P. D. Boyle, Software-controlled caches in the VMP multiprocessor, Proceedings of the 13th annual international symposium on Computer architecture, p.366-374, June 02-05, 1986, Tokyo, Japan
• 9: D. R. Cheriton , A. Gupta , P. D. Boyle , H. A. Goosen, The VMP multiprocessor: initial experience, refinements, and performance evaluation, Proceedings of the 15th Annual International Symposium on Computer architecture, p.410-421, May 30-June 02, 1988, Honolulu, Hawaii, United States
• 10: D. R. Cheriton , H. A. Goosen , P. D. Boyle, Multi-level shared caching techniques for scalability in VMP-M/C, Proceedings of the 16th annual international symposium on Computer architecture, p.16-24, April 1989, Jerusalem, Israel
• 11: Charles P. Thacker , Lawrence C. Stewart, Firefly: a multiprocessor workstation, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.164-172, October 1987, Palo Alto, California, United States
• 12: Frank S. J. "Tightly Coupled Multiprocessor System Speed Up Memory Access Time," Electronics, January 1985.
• 13: Larry Rudolph , Zary Segall, Dynamic decentralized cache schemes for mimd parallel processors, Proceedings of the 11th annual international symposium on Computer architecture, p.340-347, January 1984
• 14: Mark S. Papamarcos , Janak H. Patel, A low-overhead coherence solution for multiprocessors with private cache memories, Proceedings of the 11th annual international symposium on Computer architecture, p.348-354, January 1984
• 15: R. H. Katz , S. J. Eggers , D. A. Wood , C. L. Perkins , R. G. Sheldon, Implementing a cache consistency protocol, Proceedings of the 12th annual international symposium on Computer architecture, p.276-283, June 17-19, 1985, Boston, Massachusetts, United States
• 16: P. Sweazey , A. J. Smith, A class of compatible cache consistency protocols and their support by the IEEE futurebus, Proceedings of the 13th annual international symposium on Computer architecture, p.414-423, June 02-05, 1986, Tokyo, Japan
• 17: P. Bitar , A. M. Despain, Multiprocessor cache synchronization: issues, innovations, evolution, Proceedings of the 13th annual international symposium on Computer architecture, p.424-433, June 02-05, 1986, Tokyo, Japan
• 18: A. W. Wilson, Jr., Hierarchical cache/bus architecture for shared memory multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.244-252, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30378]
• 19: A. Goto , A. Matsumoto , E. Tick, Design and performance of a coherent cache for parallel logic programming architectures, Proceedings of the 16th annual international symposium on Computer architecture, p.25-33, April 1989, Jerusalem, Israel
• 20: C. K. Tang, "Cache Design in the Tightly Coupled Multiurocessor system," AFIPS Conference Proc., National Computer Conference, June 1976, pp.749-753.
• 21: Lucien M. Censier and Paul Feautrier, "A New Solution to Coherence Problem in Multicache Systems," IEEE Transactions on Computers, December 1978, pp. 1112-1118.
• 22: James Archibald , Jean Loup Baer, An economical solution to the cache coherence problem, Proceedings of the 11th annual international symposium on Computer architecture, p.355-362, January 1984
• 23: Wei C. Yen, David W. L. Yen, and King-Sun Fu.,"Data Coherence Problem in a Multicache System," IEEE Transactions on Computers, January 1985, pp.56-65.
• 24: C. Scheurich , M. Dubois, Correct memory operation of cache-based multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.234-243, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30377]
• 25: A. Agarwal , R. Simoni , J. Hennessy , M. Horowitz, An evaluation of directory schemes for cache coherence, Proceedings of the 15th Annual International Symposium on Computer architecture, p.280-298, May 30-June 02, 1988, Honolulu, Hawaii, United States
• 26: P. Stenström, A cache consistency protocol for multiprocessors with multistage networks, Proceedings of the 16th annual international symposium on Computer architecture, p.407-415, April 1989, Jerusalem, Israel
• 27: H. Cheong , A. V. Vaidenbaum, A cache coherence scheme with fast selective invalidation, Proceedings of the 15th Annual International Symposium on Computer architecture, p.299-307, May 30-June 02, 1988, Honolulu, Hawaii, United States
• 28: D. A. Wood , R. H. Katz, Supporting reference and dirty bits in SPUR's virtual address cache, Proceedings of the 16th annual international symposium on Computer architecture, p.122-130, April 1989, Jerusalem, Israel
• 29: G. S. Jang, F. Lai, H. C. Lee, Y. C. Maa, T. M. Parng, and J. Y. Tsai, "MARS - Multiprocessor Architecture Reconciling Symbolic with numerical Processing," International Symposium on VLSI Technology, System, and Applications, May 17-19, 1989.
• 30: Y.-C. Maa, "Designing Instruction Fetch Unit for the MARS System," Master Thesis, Computer Science Div., Dept. of Electrical Engineering, National Taiwan University, June. 1989.
• 31: W.-C. Tsai, "The Design and Implementation of Instruction Fetch Unit of the MARS System," Master Thesis, Computer Science Div., Dept. of Electrical Engineering, National Taiwan University, June, 1990.
• 32: G.-S. Jang, "The Design of Integer Processing Unit for the MARS Syatem," Master Thesis, Computer Science Div., Dept. of Electrical Engineering, National Taiwan University, June. 1989.
• 33: C.-J. Horng, "The Design and Implementation of Integer Processing Unit (IPU) for the MARS Syatem," Master Thesis, Computer Science Div., Dept. of Electrical Engineering, National Taiwan University, June. 1990.
• 34: J.-Y. Tsai, "The Design of List Processing Unit for the MARS Syatem," Master Thesis, Computer Science Div., Dept. of Electrical Engineering, National Taiwan University, June. 1989
• 35: C.-Y. Chen, "The Design and Implementation of List Processing Unit (LPU) for the MARS Syatem," Master Thesis, Computer Science Div., Dept. of Electrical Engineering, National Taiwan University, June. 1990.
• 36: L.-M. Tzeng, "MARS Performace Evaluation with Different Interconnection Networks," Master Thesis, Computer Science Div., Dept. of Electrical Engineering, National Taiwan University, June. 1989.
• 37: C. Scheurich , M. Dubois, The design of a lockup-free cache for high-performance multiprocessors, Proceedings of the 1988 ACM/IEEE conference on Supercomputing, p.352-359, November 12-17, 1988, Orlando, Florida, United States
• 38: S. J. Eggers , R. H. Katz, Evaluating the performance of four snooping cache coherency protocols, Proceedings of the 16th annual international symposium on Computer architecture, p.2-15, April 1989, Jerusalem, Israel
• 39: James Archibald , Jean-Loup Baer, Cache coherence protocols: evaluation using a multiprocessor simulation model, ACM Transactions on Computer Systems (TOCS), v.4 n.4, p.273-298, Nov. 1986 [doi>10.1145/6513.6514]