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High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator
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Source International Symposium on Microarchitecture archive
Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture table of contents
Orlando, Florida, United States
Pages: 97 - 106  
Year of Publication: 1990
ISBN:0-89791-413-9
Authors
Paul Kenyon  University Nebraska - Lincoln, Lincoln, Nebraska
Prathima Agrawal  AT&T Bell Laboratories, Murray Hill, New Jersey
Sharad Seth  University Nebraska - Lincoln, Lincoln, Nebraska
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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ABSTRACT

The development of a high-level language compiler for a micro-programmable processing element (PE) in the MARS multicomputer is described. MARS, an MIMD message passing machine, was designed to speed up VLSI CAD and similar other non-numerical applications. The need for support of a high-level language at the PE level of a multicomputer is considered, and the choice of C as an appropriate programming language is justified. Special features found in VLSI processors are examined along with compiler support for them. Conventional retargetable compiler techniques are shown to be inadequate for the highly concurrent micro-programmable PE. These techniques must be extended for microcode generation. The design of the MARS compiler is outlined. Performance data is provided to evaluate the benefit of various compiler optimizations, and to compare compiler generated microcode to hand generated microcode in terms of space and time performance


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
S. Abraham and K. Pedmanabhan. Instruction reorganisation for a variable-length pipelined microprocessor. In IEEE International Conference on Computer Derign, volume ICCD-88, 1988.
 
2
D. P. AgrawaI and J. Mauney. Structure of a paraIlehsing compiler fo:c the B-HIVE multicomputer. In Microrocesring and Microprogramming. North-Holland, 1988.
 
3
P. Agrawd, V. AgrawaI, and K. T. Cheng. Fault simulation in a pipelined multiprocessor system. In Proceedings of the IEEE International Test Conference, volume ITC-89, pages 727-734, 1989.
 
4
P. Agrawd and W. J. Dally. A hardware logic simulation system. IEEE Transactions on Computer-Aided Design, 9(1):19-29, January 1990.
 
5
P. Agrawd et al. MARS: A multiprocessorbased programmable accelerator. IEEE Design & Test of Computers, 4(5):28-36, October 1987.
 
6
7
8
9
 
10
D. K. Banerji and J. Raymond. Elements of Micro-Programming. Prentice-Hall Inc., Englewood Cliffs, NJ, 1982.
 
11
S. Chatterjee and P. Agrawd. Connected speech recognition on a multiple processor pipeline. In Proceedings of the IEEE International Conference on Acourticr, Speech, and Signal Processing, 1989.
 
12
 
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J. Fisher. Trace scheduling: a technique for global microcode compaction. IEEE Transactions on Computers, C-30(7):478-490, July 1981.
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R. Gurd. Experience developing microcode using a high level language. In Proceedings Micro- 16, 1983.
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Collaborative Colleagues:
Paul Kenyon: colleagues
Prathima Agrawal: colleagues
Sharad Seth: colleagues

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