| An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors |
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International Symposium on Microarchitecture
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Proceedings of the 26th annual international symposium on Microarchitecture
table of contents
Austin, Texas, United States
Pages: 236 - 246
Year of Publication: 1993
ISBN:0-8186-5280-2
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Authors
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Ing-Jer Huang
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Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California
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Alvin M. Despain
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Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California
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IEEE Computer Society Press
Los Alamitos, CA, USA
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Downloads (6 Weeks): 0, Downloads (12 Months): 4, Citation Count: 1
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Mauricio Breternitz, Jr. , John Paul Shen, Architecture synthesis of high-performance application-specific processors, Proceedings of the 27th ACM/IEEE conference on Design automation, p.542-548, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123398]
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Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin, Scheduling for functional pipelining and loop winding, Proceedings of the 28th conference on ACM/IEEE design automation, p.764-769, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127766]
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Mike Johnson, Superscalar Microprocessor Design, Prentice Hall, 1991
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Peter M. Kogge, The Architecture of Pipelined Computers, MacGraw-HiH, 1981
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C.-Y. Tsui , H.-T. Chen , G. Cheng , S. Liu , S. Wu , A. M. Despain , I. Pyo , C. L. Su , I.-J. Huang , K.-R. Pan , Y.-S. Koh, Application-driven design automation for microprocessor design, Proceedings of the 29th ACM/IEEE conference on Design automation, p.512-517, June 08-12, 1992, Anaheim, California, United States
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R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. Res. Dev., January 1967, pp. 25-33.
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Programming Manual for the Teledyne TDY-43 Computer, Teledyne Systems Company, 1988
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CITED BY
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Pritpal S. Ahuja , Douglas W. Clark , Anne Rogers, The performance impact of incomplete bypassing in processor pipelines, Proceedings of the 28th annual international symposium on Microarchitecture, p.36-45, November 29-December 01, 1995, Ann Arbor, Michigan, United States
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