| Register renaming and dynamic speculation: an alternative approach |
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International Symposium on Microarchitecture
archive
Proceedings of the 26th annual international symposium on Microarchitecture
table of contents
Austin, Texas, United States
Pages: 202 - 213
Year of Publication: 1993
ISBN:0-8186-5280-2
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Authors
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Mayan Moudgill
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Department of Computer Science, Cornell University, Ithaca, NY
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Keshav Pingali
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Department of Computer Science, Cornell University, Ithaca, NY
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Stamatis Vassiliadis
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School of Electrical Engineering, Cornell University, Ithaca, NY and IBM Corporation, Enterprise Systems, Poughkeepsie, NY
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IEEE Computer Society Press
Los Alamitos, CA, USA
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| Bibliometrics |
Downloads (6 Weeks): 0, Downloads (12 Months): 51, Citation Count: 33
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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Harry Dwyer , H. C. Torng, An out-of-order superscalar processor with speculative execution and fast, precise interrupts, Proceedings of the 25th annual international symposium on Microarchitecture, p.272-281, December 01-04, 1992, Portland, Oregon, United States
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W.M. Johnson. Superscalar Microprocessor Design. Prentice-Hall, Englewood Cliffs, NJ, 199 I.
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Val Popescu , Merle Schultz , John Spracklen , Gary Gibson , Bruce Lightner , David Isaman, The Metaflow Architecture, IEEE Micro, v.11 n.3, p.10-13, 63-73, May 1991
[doi> 10.1109/40.87564]
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M. D. Smith , M. Johnson , M. A. Horowitz, Limits on multiple instruction issue, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.290-302, April 03-06, 1989, Boston, Massachusetts, United States
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R.M. Tomasulo. An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of Research and Development, 11(1):25-33, January 1967.
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CITED BY 33
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Isidro Gonzalez , Marco Galluzzi , Alex Veidenbaum , Marco A. Ramirez , Adrian Cristal , Mateo Valero, A distributed processor state management architecture for large-window processors, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.11-22, November 08-12, 2008
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Akihiro Yamamoto , Yusuke Tanaka , Hideki Ando , Toshio Shimada, Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation, Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, p.33-40, September 16-16, 2007, Brasov, Romania
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Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon
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Stephen Jourdan , Ronny Ronen , Michael Bekerman , Bishara Shomar , Adi Yoaz, A novel renaming scheme to exploit value temporal locality through physical register reuse and unification, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.216-225, November 1998, Dallas, Texas, United States
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José F. Martínez , Jose Renau , Michael C. Huang , Milos Prvulovic , Josep Torrellas, Cherry: checkpointed early resource recycling in out-of-order microprocessors, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
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David W. Oehmke , Nathan L. Binkert , Trevor Mudge , Steven K. Reinhardt, How to Fake 1000 Registers, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.7-18, November 12-16, 2005, Barcelona, Spain
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R. González , A. Cristal , M. Pericas , M. Valero , A. Veidenbaum, An asymmetric clustered processor based on value content, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts
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Deniz Balkan , Joseph Sharkey , Dmitry Ponomarev , Kanad Ghose, SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
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