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MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines
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Source International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents
Austin, Texas, United States
Pages: 193 - 201  
Year of Publication: 1993
ISBN:0-8186-5280-2
Authors
Nathalie Drach  IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
André Seznec  IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
Sponsors
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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G. lrlam, SPA package, 1991
 
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A. Gonzales, J.M. Llaberia, J. Cortadella, "A Mechanism for Reducing the Cost of Branches in RISC Architectures", Microprocessing and Microprogramming 24, 1988
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"IBM RISC system/6000 technology", IBM Corporation, 1990
 
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J. Lee, A.J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", IEEE Computer,January 1984
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André Seznec: colleagues

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