| MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines |
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International Symposium on Microarchitecture
archive
Proceedings of the 26th annual international symposium on Microarchitecture
table of contents
Austin, Texas, United States
Pages: 193 - 201
Year of Publication: 1993
ISBN:0-8186-5280-2
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Authors
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Nathalie Drach
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IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
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André Seznec
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IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France
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IEEE Computer Society Press
Los Alamitos, CA, USA
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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D. R. Ditzel , H. R. McLellan , A. D. Berenbaum, The hardware architecture of the CRISP microprocessor, Proceedings of the 14th annual international symposium on Computer architecture, p.309-319, June 02-05, 1987, Pittsburgh, Pennsylvania, United States
[doi> 10.1145/30350.30385]
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A. Gonzales, J.M. Llaberia, J. Cortadella, "A Mechanism for Reducing the Cost of Branches in RISC Architectures", Microprocessing and Microprogramming 24, 1988
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