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Clocked and asynchronous instruction pipelines
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Source International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents
Austin, Texas, United States
Pages: 177 - 184  
Year of Publication: 1993
ISBN:0-8186-5280-2
Authors
Mark A. Franklin  Computer and Communication Research Center, Washington University, St. Louis, MO
Tienyo Pan  Computer and Communication Research Center, Washington University, St. Louis, MO
Sponsors
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M. Franklin and T. Pan. Performance Comparison of Clocked and Asynchronous Pipelines. Technical Report WUCCRC-92-9, Washington Univ., St. Louis, MO, 1992.
 
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P. Kogge. The Architecture o/Pipelined Computers. Hemisphere Publishing Corporation, New York, NY, 1981.
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T. Meng. Synchronization Design for Digital Systems. Kluwer Academic Publishers, Norwell, MA, 1991.
 
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T. Meng, R. Bordersen, and D. Messerschmitt. Asynchronous Design for Programmable Digital Signal Processors. IEEE Trans. Signal Proc., pages 939-952, April 1991.
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D. Wann and M. Franklin. Asynchronous and Clocked Control Structures for VLSI Based Interconnection Networks. IEEE Trans. Comput., pages 284-293, March 1983.
Collaborative Colleagues:
Mark A. Franklin: colleagues
Tienyo Pan: colleagues

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