Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	GHLP85	J. R. Goodman , Jian-tu Hsieh , Koujuch Liou , Andrew R. Pleszkun , P. B. Schechter , Honesty C. Young, PIPE: a VLSI decoupled architecture, Proceedings of the 12th annual international symposium on Computer architecture, p.20-27, June 17-19, 1985, Boston, Massachusetts, United States
	HePa90	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	John91	M. ~ohnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, New Jersey, (1991).
	Kell75	Robert M. Keller, Look-Ahead Processors, ACM Computing Surveys (CSUR), v.7 n.4, p.177-195, Dec. 1975  [doi>10.1145/356654.356657]
	Smit82	James E. Smith, Decoupled access/execute computer architectures, Proceedings of the 9th annual symposium on Computer Architecture, p.112-119, April 26-29, 1982, Austin, Texas, United States
	SmWP86	James E. Smith , Shlomo Weiss , Nicholas Y. Pang, A simulation study of decoupled architecture computers, IEEE Transactions on Computers, v.35 n.8, p.692-702, Aug. 1986  [doi>10.1109/TC.1986.1676820]
	SDVK87	J. E. Smith , G. E. Dermer , B. D. Vanderwarn , S. D. Klinger , C. M. Rozewski, The ZS-1 central processor, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.199-204, October 1987, Palo Alto, California, United States
	SmPl88	James E. Smith , Andrew R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers, v.37 n.5, p.562-573, May 1988  [doi>10.1109/12.4607]
	SoVa87	G. S. Sohi , S. Vajapeyam, Instruction issue logic for high-performance, interruptable pipelined processors, Proceedings of the 14th annual international symposium on Computer architecture, p.27-34, June 02-05, 1987, Pittsburgh, Pennsylvania, United States  [doi>10.1145/30350.30354]
	Toma67	R.M. Tomasulo, "An Efficient Algorithm for Exploi~g Multiple Arithmetic Units", IBM Journal, voL 11 Oanuary 1967), pp. 25-33.
	Wall91	David W. Wall, Limits of instruction-level parallelism, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.176-188, April 08-11, 1991, Santa Clara, California, United States

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