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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Anderson, D.W., Sparacio, F.J., and Tomasulo, R.M. The System/360 Model 91: machine philosophy and instruction handling. IBM Journal of Research and Development 11, i (January 1967), 8-24.
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Eric DeLano , Will Walker , Jeff Yetter , Mark Forsyth, A high speed superscalar PA-RISC processor, Proceedings of the thirty-seventh international conference on COMPCON, p.116-121, January 1992, San Francisco, California, United States
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Groves, R.D., and Oehler, R. An IBM second generation RISC processor architecture. In Proc. 1989 1EEE International Conference on Computer Design: VLSl in Computers and Processors, (October 1989), 134-137.
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Johnson, M. Superscalar Microprocessor Design. Prentice-Hall, Englewood Cliffs, New Jersey, 1991.
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Rau, B.R. Dynamic scheduling techniques for VLIW processors. Technical Report HPL-93-52. Hewlett- Packard Laboratories, 1993.
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Rau, B.R., Schlansker, M.S., and Yen, D.W.L. The Cydra 5 stride-insensitive memory system. In Proc. 1989 International Conference on Parallel Processing, (August 1989), 242-246.
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B. Ramakrishna Rau , David W. L. Yen , Wei Yen , Ross A. Towie, The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs, Computer, v.22 n.1, p.12-26, 28-30, 32-35, January 1989
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J. E. Smith , G. E. Dermer , B. D. Vanderwarn , S. D. Klinger , C. M. Rozewski, The ZS-1 central processor, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.199-204, October 1987, Palo Alto, California, United States
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G. S. Sohi , S. Vajapeyam, Instruction issue logic for high-performance, interruptable pipelined processors, Proceedings of the 14th annual international symposium on Computer architecture, p.27-34, June 02-05, 1987, Pittsburgh, Pennsylvania, United States
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Thornton, J.E. Parallel operation in the Control Data 6600. In Proc. AFIPS Fall Joint Computer Conference, (1964), 33-40.
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Tomasulo, R.M. An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of Research and Development 11, I (January 1967), 25-33.
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CITED BY 13
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Augustus K. Uht , Vijay Sindagi , Kelley Hall, Disjoint eager execution: an optimal form of speculative execution, Proceedings of the 28th annual international symposium on Microarchitecture, p.313-325, November 29-December 01, 1995, Ann Arbor, Michigan, United States
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Ramadass Nagarajan , Sundeep K. Kushwaha , Doug Burger , Kathryn S. McKinley , Calvin Lin , Stephen W. Keckler, Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures, Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques, p.74-84, September 29-October 03, 2004
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