| Employing finite automata for resource scheduling |
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International Symposium on Microarchitecture
archive
Proceedings of the 26th annual international symposium on Microarchitecture
table of contents
Austin, Texas, United States
Pages: 12 - 20
Year of Publication: 1993
ISBN:0-8186-5280-2
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Author
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Thomas Müller
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GMD Forschungsstelle an der Universität Karlsruhe, Vincenz-Prieβnitz-Str. 1, D-76131 Karlsruhe, Germany
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IEEE Computer Society Press
Los Alamitos, CA, USA
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Downloads (6 Weeks): 1, Downloads (12 Months): 15, Citation Count: 10
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
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David Gordon Bradlee. Retargelable Instruction Scheduling for Pipelined Processors. PhD thesis, Department of Computer Science and Engineering, University of Washington, Seattle, 1991.
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H. Emmelmann , F.-W. Schröer , L. Landwehr, BEG: a generation for efficient back ends, Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation, p.227-237, June 19-23, 1989, Portland, Oregon, United States
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Joseph A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, c-30(7):478-490, jul 1981.
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Gerry Kane. MIPS R2000 RISC Architecture. Prentice-Hall, 1988.
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