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Employing finite automata for resource scheduling
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Source International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents
Austin, Texas, United States
Pages: 12 - 20  
Year of Publication: 1993
ISBN:0-8186-5280-2
Author
Thomas Müller  GMD Forschungsstelle an der Universität Karlsruhe, Vincenz-Prieβnitz-Str. 1, D-76131 Karlsruhe, Germany
Sponsors
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Citation Count: 10
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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David Gordon Bradlee. Retargelable Instruction Scheduling for Pipelined Processors. PhD thesis, Department of Computer Science and Engineering, University of Washington, Seattle, 1991.
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Joseph A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, c-30(7):478-490, jul 1981.
 
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Gerry Kane. MIPS R2000 RISC Architecture. Prentice-Hall, 1988.
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