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Module placement on BSG-structure and IC layout applications
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Source International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 484 - 491  
Year of Publication: 1997
ISBN:0-8186-7597-7
Authors
Shigetoshi Nakatake  Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
Kunihiro Fujiyoshi  School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
Hiroshi Murata  School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)
Yoji Kajitani  Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 28,   Citation Count: 62
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ABSTRACT

A new method of packing the rectangles (modules) is presented with applications to IC layout design. It is based on the bounded-sliceline grid (BSG) structure. The BSG dissects the plane into rooms associated with binary relations ``right-to''and ``above'' such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of modules on the BSG, followed by physical realization BSG-PACK. A simulated annealing searches for a good packing of all packings by changing the assignments. Experiments showed that hundreds of rectangles are easily packed in a small rectangle area (chip) with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Remarkable examples are: the chip is not necessarily rectangle, L-shaped modules and modules which are allowed to partially overlap each other can be handled.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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W.M.Dai and E.Kuh, "Simultaneous Floorplanning and Global Routing for Hierarchical Building Block Layout", IEEE Trans. on CAD Vol.6 No.5 pp.828-837, 1987.
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Y. Kajitani, "Order of Channels for Safe Routing and Optimal Compaction of Routing Area", IEEE Trans. on CAD Vol.2 No.4 pp.293-300, 1983.
 
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H.Matsuda, S.Nakatake and Y.Kajitani, "Optimum Slicing- Structure Floorplanning with Routing Area Included", IEICE Technical Report VLD94-109 Vol.94 No.531 pp.9-14, 1995.
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Y.Shiraishi, M.Kimura, K.Kobayashi, T.Hino, M.Seriuchi, and M.Kusaoke, "A High-Packing Density Module Generator for Bipolar Analog LSIs", Proc. International Conf. on CAD pp.194-197, 1990.

CITED BY  62
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Collaborative Colleagues:
Shigetoshi Nakatake: colleagues
Kunihiro Fujiyoshi: colleagues
Hiroshi Murata: colleagues
Yoji Kajitani: colleagues

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