A design for testability technique for RTL circuits using control/data flow extraction

ABSTRACT

In this paper, we present a technique for extracting functional (control/data flow) information from register transfer level (RTL) controller/data path circuits and illustrate its use in design for hierarchical testability of these circuits. This testing procedure and design for testability (DFT) technique is general enough to handle RTL control flow intensive circuits like protocol handlers as well as data flow intensive circuits like digital filters. It makes the combined controller-data path highly testable and does not require any external behavioral information. This scheme has the advantages of low area/delay/power overheads (average of 3.2%, 0.9% and 4.1%, respectively, for benchmarks), high fault coverage (over 99% for most cases), very low test generation times (because it is independent of bit-width), and the advantage of at-speed testing. Experiments show a 2-to-4 (1-to-3) orders of magnitude test generation time advantage over an efficient gate-level sequential test generator (combinational test generator that assumes full scan).

REFERENCES

• 1: M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, IEEE Press, New York, 1990.
• 2: Kenneth D. Wagner , Sujit Dey, High-level synthesis for testability: a survey and perspective, Proceedings of the 33rd annual conference on Design automation, p.131-136, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240543]
• 3: Johannes Steensma , Francky Catthoor , Hugo De Man, Partial Scan at the Register-Transfer Level, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.488-497, October 17-21, 1993
• 4: S. Bhattacharya , S. Dey, H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads, Proceedings of the 14th IEEE VLSI Test Symposium (VTS '96), p.74, April 28-May 01, 1996
• 5: Sujit Dey , Miodrag Potkonjak, Non-scan design-for-testability of RT-level data paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.640-645, November 06-10, 1994, San Jose, California, United States
• 6: B.T. Murray and J.E Hayes, "Hierarchical test generation using precomputed tests for modules," IEEE Trans. Computer-Aided Design, vol. 9, pp. 594-603, June 1990.
• 7: Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha, Design for hierarchical testability of RTL circuits obtained by behavioral synthesis, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.173-179, October 02-04, 1995
• 8: J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991 [doi>10.1109/54.82037]
• 9: Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
• 10: Anand Raghunathan , Niraj K. Jha, An iterative improvement algorithm for low power data path synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.597-602, November 05-09, 1995, San Jose, California, United States
• 11: Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
• 12: S.T. Chakradhar, V.D. Agrawal, and S.G. Rothweiler, "A transitive closure algorithm for test generation," IEEE Trans. Computer- Aided Design, vol. 17, pp. 1015-1028,July 1993.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
  B.6 LOGIC DESIGN
      B.6.2 Reliability and Testing**
          Subjects: Test generation**

General Terms:
Design, Experimentation, Reliability