Validation coverage analysis for complex digital designs

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Validation coverage analysis for complex digital designs

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International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 146 - 151

Year of Publication: 1997

ISBN:0-8186-7597-7

Authors

Richard C. Ho	Computer Systems Laboratory, Stanford University, Stanford, CA
Mark A. Horowitz	Computer Systems Laboratory, Stanford University, Stanford, CA

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 13, Citation Count: 18

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ABSTRACT

In interactive behavioral synthesis, the designer can control the design process at every stage, including modifying the schedule of the design to improve its performance. In this paper, we present a methodology for performance optimization in interactive behavioral synthesis. Also proposed are several quality metrics and hints that can assist the user in utilizing the proposed methodology. When the user is optimizing the performance of the design, one important decision is the selection of a clock period. To facilitate clock selection by the user, we have developed an algorithm to estimate the effect of different clock periods on the execution time of the design. We have tested our methodology on several benchmarks. The experimental results support the proposed methodology by demonstrating an average improvement of 46.2% in design performance.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 18

	Dinos Moundanos , Jacob A. Abraham, On Design Validation Using Verification Technology, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.173-189, August-October 1999
	Chien-Nan Jimmy Liu , Jing-Yang Jou, An Automatic Controller Extractor for HDL Descriptions at the RTL, IEEE Design & Test, v.17 n.3, p.72-77, July 2000
	Jules P. Bergmann , Mark A. Horowitz, Improving coverage analysis and test generation for large designs, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.580-583, November 07-11, 1999, San Jose, California, United States
	Chia-Chih Yen , Jing-Yang Jou , Kuang-Chien Chen, A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation, IEEE Design & Test, v.21 n.2, p.111-120, March 2004
	Jules P. Bergmann , Mark A. Horowitz, Vex—A CAD toolbox, Proceedings of the 36th ACM/IEEE conference on Design automation, p.523-528, June 21-25, 1999, New Orleans, Louisiana, United States
	Jayanta Bhadra , Magdy S. Abadir , Li-C. Wang , Sandip Ray, A Survey of Hybrid Techniques for Functional Verification, IEEE Design & Test, v.24 n.2, p.112-122, March 2007
	Yi Feng , Zheng Zhou , Dong Tong , Xu Cheng, Clock domain crossing fault model and coverage metric for validation of SoC design, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Tai-Ying Jiang , Chien-Nan Jimmy Liu , Jing-Yang Jou, An observability measure to enhance statement coverage metric for proper evaluation of verification completeness, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Cássio L. Rodrigues , Karina R. G. da Silva , Henrique N. Cunha, Improving functional verification of embedded systems using hierarchical composition and set theory, Proceedings of the 2009 ACM symposium on Applied Computing, March 08-12, 2009, Honolulu, Hawaii
	Sadik Ezer , Scott Johnson, Smart diagnostics for configurable processor verification, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Serdar Tasiran , Kurt Keutzer, Coverage Metrics for Functional Validation of Hardware Designs, IEEE Design & Test, v.18 n.4, p.36-45, July 2001
	Pei Hsin Ho , Thomas Shiple , Kevin Harer , James Kukula , Robert Damiano , Valeria Bertacco , Jerry Taylor , Jiang Long, Smart simulation using collaborative formal and simulation engines, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Smitha Shyam , Valeria Bertacco, Distance-guided hybrid verification with GUIDO, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Malay K. Ganai , Adnan Aziz , Andreas Kuehlmann, Enhancing simulation with BDDs and ATPG, Proceedings of the 36th ACM/IEEE conference on Design automation, p.385-390, June 21-25, 1999, New Orleans, Louisiana, United States
	David Van Campenhout , Trevor Mudge , John P. Hayes, High-level test generation for design verification of pipelined microprocessors, Proceedings of the 36th ACM/IEEE conference on Design automation, p.185-188, June 21-25, 1999, New Orleans, Louisiana, United States
	Malay Ganai , Praveen Yalagandula , Adnan Aziz , Andreas Kuehlmann , Vigyan Singhal, SIVA: A System for Coverage-Directed State Space Search, Journal of Electronic Testing: Theory and Applications, v.17 n.1, p.11-27, February 2001
	Hana Chockler , Orna Kupferman , Moshe Y. Vardi, Coverage metrics for temporal logic model checking, Formal Methods in System Design, v.28 n.3, p.189-212, May 2006
	Jian Shen , Jacob A. Abraham, An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.67-81, Feb/April 2000