Sensitivity analysis of iterative design processes

ABSTRACT

As design processes continue to increase in complexity, it is important to base process improvements on quantitative analysis. In this paper we develop an analytical approach to analyze sequential design processes using sensitivity analysis. Two applications illustrate this approach, one involving a Pareto analysis of an ASIC design process and the other an optimization of a software design process to determine the lower bound of the process completion time.

REFERENCES

• 1: S.W. Director and R. A. Rohrer, "Automated Network Design, The Frequency Domain Case," IEEE Transactions on Circuit Theo~7, vol. CT-16, pp. 330-337, August 1969.
• 2: Eric W. Johnson , Luis A. Castillo , Jay B. Brockman, Application of a Markov model to the measurement, simulation, and diagnosis of an iterative design process, Proceedings of the 33rd annual conference on Design automation, p.185-188, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240553]
• 3: E.W. Johnson and J. B. Brockman, "Improving Sequential Design Processes using Sensitivity Analysis," Department of Computer Science and Engineering Technical Report #96-1, University of Notre Dame, 1996.
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

          Nouns: ASIC

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.8 Metrics
          Subjects: Performance measures

General Terms:
Design, Performance

Keywords:
Design Process Improvement, Sensitivity Analysis