Timing verification of sequential domino circuits

ABSTRACT

Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An important observation is that input signals to domino gates may start changing near the end of the evaluate phase. The first method models domino gates explicitly, similar to latches. The second method treats domino gates only during pre- and post-processing steps. This method is shown to be more conservative, but easier to compute.

REFERENCES

• 1: R.H. Krambeck, Charles M. Lee, and Hung-Fai Stephen Law, "High-Speed Compact Circuits with CMOS," IEEE Journal of Solid-State Circuits; Vol. 17, No. 3, June 1982. p 614-619; 1982.
• 2: K. Venkat et al, "Timing verification of dynamic circuits," Proceedings of the Custom Integrated Circuits Conference 1995. p271-274; 1995.
• 3: K. Sakallah, T. Mudge, O. Olukotun, "checkTc and minTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits," in ICCAD-90 Digest of Technical Papers, pp. 552-555, November 1990.
• 4: K. Sakallah, T. Mudge, O. Olukotun, "Analysis and Design of Latch-Controlled Synchronous Digital Circuits," IEEE Trans. on Computer-Aided Design, Vol. 11, No. 3, pp. 322-333, March 1992.
• 5: Timothy M. Burks , Karem A. Sakallah , Trevor N. Mudge, Critical paths in circuits with level-sensitive latches, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.273-291, June 1995 [doi>10.1109/92.386227]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Verification

General Terms:
Design, Verification

Keywords:
domino gates, input signals, logic testing, sequential domino circuits, static timing verification