Algorithms for address assignment in DSP code generation

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Algorithms for address assignment in DSP code generation

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International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 109 - 112

Year of Publication: 1997

ISBN:0-8186-7597-7

Authors

Rainer Leupers	University of Dortmund, Department of Computer Science 12, 44221 Dortmund, Germany
Peter Marwedel	University of Dortmund, Department of Computer Science 12, 44221 Dortmund, Germany

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 13, Citation Count: 41

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ABSTRACT

This paper presents DSP code optimization techniques, which originate from dedicated memory address generation hardware. We define a generic model of DSP address generation units. Based on this model, we present efficient heuristics for computing memory layouts for program variables, which optimize utilization of parallel address generation units. Improvements and generalizations of previous work are described, and the efficacy of the proposed algorithms is demonstrated through experimental evaluation.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 41

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	Sathishkumar Udayanarayanan , Chaitali Chakrabarti, Energy-efficient code generation for DSP56000 family (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.247-249, July 25-27, 2000, Rapallo, Italy
	Sungtaek Lim , Jihong Kim , Kiyoung Choi, Scheduling-based code size reduction in processors with indirect addressing mode, Proceedings of the ninth international symposium on Hardware/software codesign, p.165-169, April 2001, Copenhagen, Denmark
	Wei-Kai Cheng , Youn-Long Lin, Addressing optimization for loop execution targeting DSP with auto-increment/decrement architecture, Proceedings of the 11th international symposium on System synthesis, p.15-20, December 02-04, 1998, Hsinchu, Taiwan, China
	Erik Eckstein , Andreas Krall, Minimizing cost of local variables access for DSP-processors, ACM SIGPLAN Notices, v.34 n.7, p.20-27, July 1999
	Sean Leventhal , Lin Yuan , Neal K. Bambha , Shuvra S. Bhattacharyya , Gang Qu, DSP address optimization using evolutionary algorithms, Proceedings of the 2005 workshop on Software and compilers for embedded systems, p.91-98, September 29-October 01, 2005, Dallas, Texas
	A. Basu , R. Leupers , P. Marwedel, Register-constrained address computation in DSP programs, Proceedings of the conference on Design, automation and test in Europe, p.929-930, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Ashok Sudarsanam , Stan Liao , Srinivas Devadas, Analysis and evaluation of address arithmetic capabilities in custom DSP architectures, Proceedings of the 34th annual conference on Design automation, p.287-292, June 09-13, 1997, Anaheim, California, United States
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	V. V. Rubanov , A. I. Grinevich , D. A. Markovtsev, Specific optimization features in a C compiler for DSPs, Programming and Computing Software, v.32 n.1, p.19-30, January 2006
	G. Chen , M. Kandemir , M. J. Irwin , J. Ramanujam, Reducing code size through address register assignment, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.1, p.225-258, February 2006
	J. Ramanujam , Satish Krishnamurthy , Jinpyo Hong , Mahmut Kandemir, Address Code and Arithmetic Optimizations for Embedded Systems, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.619, January 07-11, 2002
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