Simulation-based techniques for dynamic test sequence compaction

ABSTRACT

Simulation-based techniques for dynamic compaction of test sequences are proposed. The first technique uses a fault simulator to remove test vectors from the partially-specified test sequence generated by a deterministic test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in the partially-specified test sequence in order to increase the number of faults detected by the sequence. Significant reductions in test set sizes were observed for all benchmark circuits studied. Fault coverages improved for many of the circuits, and execution times often dropped as well, since fewer faults had to be targeted by the computation-intensive deterministic test generator.

REFERENCES

• 1: T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, "Test compaction for sequential circuits," IEEE Trans. Computer-Aided Design,, vol. 11, no. 2, pp. 260-267, Feb. 1992.
• 2: Irith Pomeranz , Sudhakar M. Reddy, On static compaction of test sequences for synchronous sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.215-220, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240558]
• 3: Irith Pomeranz , Sudhakar M. Reddy, On generating compact test sequences for synchronous sequential circuits, Proceedings of the conference on European design automation, p.105-110, September 18-22, 1995, Brighton, England
• 4: Srimat T. Chakradhar , Anand Raghunathan, Bottleneck removal algorithm for dynamic compaction and test cycles reduction, Proceedings of the conference on European design automation, p.98-104, September 18-22, 1995, Brighton, England
• 5: Anand Raghunathan , Srimat T. Chakradhar, Acceleration techniques for dynamic vector compaction, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.310-317, November 05-09, 1995, San Jose, California, United States
• 6: A. Raghunathan , S. T. Chakradhar, Dynamic test Sequence compaction for Sequential Circuits, Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, p.170, January 03-06, 1996
• 7: T. J. Lambert , K. K. Saluja, Methods for Dynamic Test Vector compaction in Sequential Test Generation, Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, p.166, January 03-06, 1996
• 8: I. Pomeranz , S. M. Reddy, Dynamic test compaction for synchronous sequential circuits using static compaction techniques, Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96), p.53, June 25-27, 1996
• 9: Roberto Bevacqua , Luca Guerrazzi , Fabrizio Ferrandi , Franco Fummi, Implicit Test Sequences Compaction for Decreasing Test Application Cos, Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors, p.384-382, October 07-09, 1996
• 10: E. M. Rudnick , J. H. Patel, A genetic approach to test application time reduction for full scan and partial scan circuits, Proceedings of the 8th International Conference on VLSI Design, p.288, January 04-07, 1995
• 11: David E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1989
• 12: Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
• 13: T. P. Kelsey , K. K. Saluja , S. Y. Lee, An Efficient Algorithm for Sequential Circuit Test Generation, IEEE Transactions on Computers, v.42 n.11, p.1361-1371, November 1993 [doi>10.1109/12.247839]
• 14: T. M. Niermann, W.-T. Cheng, and J. H. Patel, "PROOFS: A fast, memory-eificient sequential circuit fault simulator," IEEE Trans. Computer-Aided Design, vol. 11, no. 2, pp. 198-207, Feb. 1992.
• 15: F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," Int. Symposium on Circuits and Systems, pp. 1929-1934, May 1989.
• 16: Elizabeth M. Rudnick , Janak H. Patel , Gary S. Greenstein , Thomas M. Niermann, Sequential circuit test generation in a genetic algorithm framework, Proceedings of the 31st annual conference on Design automation, p.698-704, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196619]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN

General Terms:
Design, Performance

Keywords:
dynamic test compaction, compact test sets, sequential circuit test generation, genetic algorithms