| A new method towards achieving global optimality in technology mapping |
| Full text |
Publisher Site
,
Pdf
(536 KB)
|
| Source
|
International Conference on Computer Aided Design
archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California, United States
Pages: 9 - 12
Year of Publication: 1997
ISBN:0-8186-7597-7
|
|
Authors
|
|
Wen Xiaoqing
|
Dept. of Information Engr., Akita University, Akita 010, Japan
|
|
Kewal K. Saluja
|
Dept. of Electrical & Computer Engr., University of Wisconsin-Madison, Madison, WI
|
|
| Sponsors |
|
| Publisher |
IEEE Computer Society
Washington, DC, USA
|
| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 0
|
|
|
ABSTRACT
This paper presents a new method for covering a Boolean network by library cells. In this method, matches are classified according to their properties. Some matches are selected unconditionally into a cover and the remaining nodes are divided into independent portions. Then, a match compatibility graph (MCG) is constructed for each portion and an optimum cover is found for it using the MCG. Thus, our method finds an efficient and closer to optimum cover for the complete network.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
 |
2
|
|
| |
3
|
E. Detjens,. G. Grannot, R. Rundell, A. San~iovanni, and A. Wang, "Technology Mapping in MIS," Proc. ICCAD, pp. 116-119, 1987.
|
| |
4
|
R. Bergamaschi, "SKOL: A System for Logic Synthesis and Technology Mapping," IEEE Trans. Computer-Aided Design, vol. CAD-10, pp. 1342-1355, Nov. 1991.
|
| |
5
|
K. ChamthatT and M. Pedtam, "Computing the Area versus Delay Trade-Off Curves in Technology Mapping, Trads. Computer-Aided Design, vol. CAD-14, pp. 1480- 1489, De~. 1995.
|
| |
6
|
David Gregory , Karen Bartlett , Aart de Geus , Gary Hachtel, SOCRATES: a system for automatically synthesizing and optimizing combinational logic, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.79-85, July 1986, Las Vegas, Nevada, United States
|
| |
7
|
M. Kahrsb "Matching a Parts Library in a Silicon Compiler, Proc. ICCAD, pp. 169-171, I987.
|
| |
8
|
F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. ISCAS'85, 1985.
|
|