| A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 33rd annual Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 527 - 532
Year of Publication: 1996
ISBN:0-89791-779-0
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Authors
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Nguyen Ngoc Bình
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Department of Information and Computer Sciences, Faculty of Engineering Science, Osaka University, Toyonaka-shi, Osaka, 560 Japan and Dept. of Information & Computer Sciences, Toyohashi University of Technology, Toyohashi, 441 Japan
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Masaharu Imai
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Department of Information and Computer Sciences, Faculty of Engineering Science, Osaka University, Toyonaka-shi, Osaka, 560 Japan and Dept. of Information & Computer Sciences, Toyohashi University of Technology, Toyohashi, 441 Japan
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Akichika Shiomi
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Department of Computer Science, Faculty of Information, Shizuoka University, Hamamatsu-shi, 432 Japan and Dept. of Information & Computer Sciences, Toyohashi University of Technology, Toyohashi, 441 Japan
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Nobuyuki Hikichi
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Dept. of Software Technology, Software Research Associates, Inc., Tokyo, 170 Japan
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 12
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J. Sato, A. Alomary, Y. Honma, T. Nakata, A. Shiomi, N. Hikichi, and M. Imai, "PEAS-I: A Hardware/Software Codesign System for ASIP Development," IEICE Trans. Fundamentals, vol.E77-A, no.3, pp. 483 -491, Mar. 1994.
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N.N. Binh, M. Imai, A. Shiomi, and N. Hikichi: "A Pipeline Scheduling Algorithm for Instruction Set Processor Design Optimization," Proc. of APCHDL'94, pp. 59- 66, Toyohashi, Japan, Oct. 1994.
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Masaharu Imai , Jun Sato , Alauddin Alomary , Nobuyuki Hikichi, An integer programming approach to instruction implementation method selection problem, Proceedings of the conference on European design automation, p.106-111, November 1992, Congress Centrum Hamburg, Hamburg, Germany
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Alauddin Alomary , Takeharu Nakata , Yoshimichi Honma , Masaharu Imai , Nobuyuki Hikichi, An ASIP instruction set optimization algorithm with functional module sharing constraint, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.526-532, November 07-11, 1993, Santa Clara, California, United States
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A. Alomary, T. Nakata, Y. Honma, A. Shiomi, M. Imai, and N. Hikichi: "An ASIP Instruction Set Optimization Algorithm with Execution Cycle Constraint," Proc. of the 4th Synthesis And Simulation Meeting and international Interchange (SASIMI' 93 ), pp. 34 - 43, Nara, Japan, Oct. 1993.
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R. Stallman: Using and Porting GNU CC, Free Software Foundation, Version 1.40, 1991.
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Y. Nakamura, K. Oguri, A. Nagoya: "Synthesis from Pure Behavioral Descriptions," in High-Level VLSI Synthesis, Camposano, R., and Wolf, W., eds, pp. 205-229, Kluwer Academic Publishers, 1991.
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Nguyen Ngoc Binh , Masaharu Imai , Akichika Shiomi , Nobuyuki Hikichi, A hardware/software codesign method for pipelined instruction set processor using adaptive database, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.14-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan
[doi> 10.1145/224818.224845]
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CITED BY 12
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Koichi Tachikake , Nozomu Togawa , Yuichiro Miyaoka , Jinku Choi , Masao Yanagisawa , Tatsuo Ohtsuki, A hardware/software partitioning algorithm for SIMD processor cores, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
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Yuichiro Miyaoka , Yoshiharu Kataoka , Nozomu Togawa , Massao Yanagisawa , Tatsuo Ohtsuki, Area/delay estimation for digital signal processor cores, Proceedings of the 2001 conference on Asia South Pacific design automation, p.156-161, January 2001, Yokohama, Japan
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Yuichiro Miyaoka , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki, A cosynthesis algorithm for application specific processors with heterogeneous datapaths, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.250-255, January 27-30, 2004, Yokohama, Japan
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Barry Shackleford , Mitsuhiro Yasuda , Etsuko Okushi , Hisao Koizumi , Hiroyuki Tomiyama , Hiroto Yasuura, Memory-CPU size optimization for embedded system designs, Proceedings of the 34th annual conference on Design automation, p.246-251, June 09-13, 1997, Anaheim, California, United States
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