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A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 527 - 532  
Year of Publication: 1996
ISBN:0-89791-779-0
Authors
Nguyen Ngoc Bình  Department of Information and Computer Sciences, Faculty of Engineering Science, Osaka University, Toyonaka-shi, Osaka, 560 Japan and Dept. of Information & Computer Sciences, Toyohashi University of Technology, Toyohashi, 441 Japan
Masaharu Imai  Department of Information and Computer Sciences, Faculty of Engineering Science, Osaka University, Toyonaka-shi, Osaka, 560 Japan and Dept. of Information & Computer Sciences, Toyohashi University of Technology, Toyohashi, 441 Japan
Akichika Shiomi  Department of Computer Science, Faculty of Information, Shizuoka University, Hamamatsu-shi, 432 Japan and Dept. of Information & Computer Sciences, Toyohashi University of Technology, Toyohashi, 441 Japan
Nobuyuki Hikichi  Dept. of Software Technology, Software Research Associates, Inc., Tokyo, 170 Japan
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 14,   Citation Count: 12
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J. Sato, A. Alomary, Y. Honma, T. Nakata, A. Shiomi, N. Hikichi, and M. Imai, "PEAS-I: A Hardware/Software Codesign System for ASIP Development," IEICE Trans. Fundamentals, vol.E77-A, no.3, pp. 483 -491, Mar. 1994.
 
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N.N. Binh, M. Imai, A. Shiomi, and N. Hikichi: "A Pipeline Scheduling Algorithm for Instruction Set Processor Design Optimization," Proc. of APCHDL'94, pp. 59- 66, Toyohashi, Japan, Oct. 1994.
 
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A. Alomary, T. Nakata, Y. Honma, A. Shiomi, M. Imai, and N. Hikichi: "An ASIP Instruction Set Optimization Algorithm with Execution Cycle Constraint," Proc. of the 4th Synthesis And Simulation Meeting and international Interchange (SASIMI' 93 ), pp. 34 - 43, Nara, Japan, Oct. 1993.
 
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R. Stallman: Using and Porting GNU CC, Free Software Foundation, Version 1.40, 1991.
 
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Y. Nakamura, K. Oguri, A. Nagoya: "Synthesis from Pure Behavioral Descriptions," in High-Level VLSI Synthesis, Camposano, R., and Wolf, W., eds, pp. 205-229, Kluwer Academic Publishers, 1991.
 
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CITED BY  12
 
 
 
 
 
 
 

Collaborative Colleagues:
Nguyen Ngoc Bình: colleagues
Masaharu Imai: colleagues
Akichika Shiomi: colleagues
Nobuyuki Hikichi: colleagues

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