|
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
M.S. Abadir and M.A. Breuer, "A Knowledge Based System for Designing Testable VLSI Chips," IEEE Design & Test of Computers, 2(4):56- 68, August 1985.
|
| |
2
|
J.R. Armstrong, "Hierarchical Test Generation: Where We Are, And Where We Should Be Going," Proc. EURO-DAC, pp. 434-439, 1993.
|
| |
3
|
|
| |
4
|
|
| |
5
|
R.G. Bennetts, Guest editor, "Metamorphosis in Design: Test Synthesis," IEEE Design & Test of Computers, Vol. 12, No. 2, Summer 1995.
|
| |
6
|
R.G. Bennetts and K.D. Wagner, "Test Synthesis: Towards Higher Levels of Abstraction, Proc. Electronic Design Automation & Test Conference, Asia, 1995.
|
| |
7
|
S. Bhatia and N. K. Jha, "Genesis: A Behavioral Synthesis System for Hierarchical Testability," Proc. European Design and Test Conference, 1994.
|
| |
8
|
S. Bhattacharya, F. Brglez, and S. Dey, "Transformations and Resynthesis for Testability of RTL Control-Data Path Specifications," IEEE Transactions on VLSI Systems, 1 (3):304-318, Sept. 1993.
|
| |
9
|
C.-H. Chen, T. Karnik, and D.G. Saab, "Structural and Behavioral Synthesis for Testability Techniques," IEEE Transactions on Computer- Aided Design, 13(6):777-785, June 1994.
|
| |
10
|
|
| |
11
|
V. Chickermane, J.Lee, and J.H. Patel, "Addressing Design for Testability at the Architectural Level," IEEE Transactions on Computer- Aided Design, 13(7):920-934, July 1994.
|
| |
12
|
|
| |
13
|
|
| |
14
|
Sujit Dey , Vijay Gangaram , Miodrag Potkonjak, A controller-based design-for-testability technique for controller-data path circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.534-540, November 05-09, 1995, San Jose, California, United States
|
| |
15
|
|
| |
16
|
|
| |
17
|
|
| |
18
|
|
| |
19
|
|
 |
20
|
|
| |
21
|
B. Konemann, J. Mucha, and G. Zwiehoff, "Built-In Logic Block Observation Techniques," Proc. Int' 1 Test Conference, pp. 37-41, 1979.
|
| |
22
|
D.H. Lee and S.M. Reddy, "On Determining Scan Flip-Flops in Partial-Scan Designs," Proc. Int' 1 Conference on Computer-Aided Design, pp. 322-325, 1990.
|
| |
23
|
J. Lee and J.H. Patel, "Architectural Level Test Generation for Microprocessors," IEEE Trans. on Computer-Aided Design, 13(10): 1288- 1300, Oct. 1994.
|
 |
24
|
Tien-Chien Lee , Niraj K. Jha , Wayne H. Wolf, Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments, Proceedings of the 30th international conference on Design automation, p.292-297, June 14-18, 1993, Dallas, Texas, United States
[doi> 10.1145/157485.164897]
|
| |
25
|
|
| |
26
|
|
| |
27
|
|
| |
28
|
|
| |
29
|
B.T. Murray and J.E Hayes, "Hierarchical Test Generation Using Precomputed Tests for Modules," Proc. Int'l Test Conf., pp. 221-229, 1988.
|
| |
30
|
|
 |
31
|
Christos A. Papachristou , Scott Chiu , Haidar Harmanani, A data path synthesis method for self-testable designs, Proceedings of the 28th conference on ACM/IEEE design automation, p.378-384, June 17-22, 1991, San Francisco, California, United States
[doi> 10.1145/127601.127698]
|
 |
32
|
Ishwar Parulkar , Sandeep Gupta , Melvin A. Breuer, Data path allocation for synthesizing RTL design with low BIST area overhead, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.395-401, June 12-16, 1995, San Francisco, California, United States
[doi> 10.1145/217474.217561]
|
| |
33
|
M. Potkonjak, S. Dey, and R. Roy, "Behavioral Synthesis of Area-Efficient Testable Designs Using Interaction Between Hardware Sharing and Partial Scan," IEEE Transactions on Computer-Aided Design, 14(9):1141-1154, Sept. 1995.
|
| |
34
|
M. Potkonjak, S. Dey and R. Roy," Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints," IEEE Transactions on Computer-Aided Design, 14(5):531-546,1995.
|
| |
35
|
J. Steensma, F. Catthoor, and H. De Man, "Partial Scan at the Register- Transfer Level," Proc. Int' l Test Conf., 1991.
|
| |
36
|
Test Synthesis Seminar, Digest of Papers, IEEE Int'l Test Conference, 1994.
|
| |
37
|
P. Vishakantaiah , J. Abraham , M. Abadir, Automatic test knowledge extraction from VHDL (ATKET), Proceedings of the 29th ACM/IEEE conference on Design automation, p.273-278, June 08-12, 1992, Anaheim, California, United States
|
| |
38
|
|
| |
39
|
E Vishakantaiah, T. Thomas, J.A. Abraham, and M.S. Abadir, "AMBI- ANT: Automatic Generation of Behavioral Modifications for Testability," Proc. ICCD, pp. 63-66, 1993.
|
| |
40
|
|
CITED BY 13
|
|
|
|
|
|
|
|
Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha, A design for testability technique for RTL circuits using control/data flow extraction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.329-336, November 10-14, 1996, San Jose, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A. Antola , V. Piuri , M. Sami, A low-redundancy approach to semi-concurrent error detection in data paths, Proceedings of the conference on Design, automation and test in Europe, p.266-272, February 23-26, 1998, Le Palais des Congrés de Paris, France
|
|
|
|
|
|
|
|
|
|
|
|
Peer to Peer - Readers of this Article have also read:
-
Data structures for quadtree approximation and compression
Communications of the ACM
28, 9
Hanan Samet
-
A hierarchical single-key-lock access control using the Chinese remainder theorem
Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing
Kim S. Lee
, Huizhu Lu
, D. D. Fisher
-
The GemStone object database management system
Communications of the ACM
34, 10
Paul Butterworth
, Allen Otis
, Jacob Stein
-
Putting innovation to work: adoption strategies for multimedia communication systems
Communications of the ACM
34, 12
Ellen Francik
, Susan Ehrlich Rudman
, Donna Cooper
, Stephen Levine
-
An intelligent component database for behavioral synthesis
Proceedings of the 27th ACM/IEEE Design Automation Conference on
Gwo-Dong Chen
, Daniel D. Gajski
|