Characterization and parameterized random generation of digital circuits

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Characterization and parameterized random generation of digital circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 33rd annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 94 - 99

Year of Publication: 1996

ISBN:0-89791-779-0

Authors

Michael Hutton	Departments of Computer Science, University of Toronto, Ontario M5S 1A4
J. P. Grossman	Departments of Mathematics, University of Toronto, Ontario M5S 1A4
Jonathan Rose	Departments of Electrical and Computer Engineering, University of Toronto, Ontario M5S 1A4
Derek Corneil	Departments of Computer Science, University of Toronto, Ontario M5S 1A4

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 15, Citation Count: 17

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	V. Betz, On biased and non-uniform global routing architectures and CAD tools for FPGAs. Tech. Report in preparation. University of Toronto, 1996.
	2	J. Cong and Y. Ding, FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs, IEEE Trans. CAD, 13 (June, 1994), pp. 1-12.
	3	Joel Darnauer , Wayne Wei-Ming Dai, A method for generating random circuits and its application to routability measurement, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.66-72, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228380]
	4	E. R. Gansner , E. Koutsofios , S. C. North , K.-P. Vo, A Technique for Drawing Directed Graphs, IEEE Transactions on Software Engineering, v.19 n.3, p.214-230, March 1993 [doi>10.1109/32.221135]
	5	Michael David Hutton , Jonathan Rose , Derek Corneil, Characterization and parameterized generation of digital circuits, 1997
	6	M. D. Hutton and J. S. Rose, Automatic Generation of Hierarchical Digital Circuit Systems. Tech. Report in preparation. University of Toronto, 1996.
	7	B. S. Landman and R. L. Russo, On a Pin Versus Block Relationship for Partitions of Logic Graphs, IEEE Trans. Comp., C-20 (1971), pp. 1469-1479.
	8	Programmable Electronics Performance Corporation, PREP PLD Benchmark Suite#l, V1.2. 504 Nino Ave. Los Gatos, CA 95032, 1993.
	9	E. M. Sentovich et. al, SIS: A System for Sequential Circuit Analysis. Tech. Report No. UCB/ERL M92/41. University of California, Berkeley, 1992.
	10	S. Yang, Logic Synthesis and Optimization Benchmarks, Version 3.0. Tech. Report. Microelectronics Centre of North Carolina. P.O. Box 12889, Research Triangle Park, NC 27709 USA, 1991.

CITED BY 17

	D. Ghosh , N. Kapur , J. Harlow, III , F. Brglez, Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking, Proceedings of the conference on Design, automation and test in Europe, p.656-663, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Nevin Kapur , Debabrata Ghosh , Franc Brglez, Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions, Proceedings of the 1997 international symposium on Physical design, p.136-143, April 14-16, 1997, Napa Valley, California, United States
	Christopher Inacio , Herman Schmit , David Nagle , Andrew Ryan , Donald E. Thomas , Yingfai Tong , Ben Klass, Vertical benchmarks for CAD, Proceedings of the 36th ACM/IEEE conference on Design automation, p.408-413, June 21-25, 1999, New Orleans, Louisiana, United States
	Shankar Balachandran , Dinesh Bhatia, A-priori wirelength and interconnect estimation based on circuit characteristics, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Michael Hutton , Jonathan Rose , Derek Corneil, Generation of synthetic sequential benchmark circuits, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.149-155, February 09-11, 1997, Monterey, California, United States
	Douglas Chang , Malgorzata Marek-Sadowska, Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.142-148, February 09-11, 1997, Monterey, California, United States
	Joachim Pistorius , Edmée Legai , Michel Minoux, Generation of very large circuits to benchmark the partitioning of FPGA, Proceedings of the 1999 international symposium on Physical design, p.67-73, April 12-14, 1999, Monterey, California, United States
	Jason Cong , Michail Romesis , Min Xie, Optimality and Stability Study of Timing-Driven Placement Algorithms, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.472, November 09-13, 2003
	Steven J. E. Wilton, SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.171-178, February 22-25, 1998, Monterey, California, United States
	Lech Józwiak, Benchmarking in digital circuit design, Proceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics, p.58-66, May 27-30, 2008, Istanbul, Turkey
	Charles J. Alpert, The ISPD98 circuit benchmark suite, Proceedings of the 1998 international symposium on Physical design, p.80-85, April 06-08, 1998, Monterey, California, United States
	Mukul R. Prasad , Philip Chong , Kurt Keutzer, Why is ATPG easy?, Proceedings of the 36th ACM/IEEE conference on Design automation, p.22-28, June 21-25, 1999, New Orleans, Louisiana, United States
	Mohammed A. S. Khalid , Jonathan Rose, A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.45-54, February 22-25, 1998, Monterey, California, United States
	Frank M. Johannes, Partitioning of VLSI circuits and systems, Proceedings of the 33rd annual conference on Design automation, p.83-87, June 03-07, 1996, Las Vegas, Nevada, United States
	Lech Józwiak , Dominik Gawłowski , Aleksander Slusarczyk, Benchmarking in digital circuit design automation, WSEAS Transactions on Circuits and Systems, v.7 n.4, p.287-310, April 2008
	Arifur Rahman , Shamik Das , Anantha P. Chandrakasan , Rafael Reif, Wiring requirement and three-dimensional integration technology for field programmable gate arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.44-54, February 2003
	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Design and implementation of move-based heuristics for VLSI hypergraph partitioning, Journal of Experimental Algorithmics (JEA), 5, p.5-es, 2000