Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. H. L. Aarts , G. Essink , E. A. de Kock, Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors, Proceedings of the 1996 European conference on Design and Test, p.460, March 11-14, 1996
	2	Charles J. Alpert and Andrew B. Kahng. Multiway partitioning via geometric embeddings, orderings, and dynamic programming. Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14:1342-1358, 1995.
	3	Charles J. Alpert , Andrew B. Kahng, Recent directions in netlist partitioning: a survey, Integration, the VLSI Journal, v.19 n.1-2, p.1-81, Aug. 1995  [doi>10.1016/0167-9260(95)00008-4]
	4	Charles J. Alpert , So-Zen Yao, Spectral partitioning: the more eigenvectors, the better, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.195-200, June 12-16, 1995, San Francisco, California, United States  [doi>10.1145/217474.217529]
	5	Daniel Brasen and Gabri61e Saucier. FPGA partitioning for critical paths. In The Eu~vpean Design and Test Conference (EDTC), pages 99-103. IEEE, 1994.
	6	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral-based multi-way FPGA partitioning, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.133-139, February 12-14, 1995, Monterey, California, United States  [doi>10.1145/201310.201331]
	7	David Ihsin Cheng , Chih-Chang Lin , Malgorzata Marek-Sadowska, Circuit partitioning with logic perturbation, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.650-655, November 05-09, 1995, San Jose, California, United States
	8	Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, and Rodney Lindelof. Local ratio cut and set covering partitioning for huge logic emulation systems. Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14:1085-1092, 1995.
	9	Jason Cong , Zheng Li , Rajive Bagrodia, Acyclic multi-way partitioning of Boolean networks, Proceedings of the 31st annual conference on Design automation, p.670-675, June 06-10, 1994, San Diego, California, United States  [doi>10.1145/196244.196609]
	10	Sujit Dey , Franc Brglez , Gershon Kedem, Corolla based circuit partitioning and resynthesis, Proceedings of the 27th ACM/IEEE conference on Design automation, p.607-612, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123416]
	11	W.E. Donath. Logic partitioning. In B. Preas and M. Lorenzetti, editors, Physical Design Automation in VLSI Systems. Benjamin/Cummings, 1988.
	12	Shantanu Dutt , Wenyong Deng, A probability-based approach to VLSI circuit partitioning, Proceedings of the 33rd annual conference on Design automation, p.100-105, June 03-07, 1996, Las Vegas, Nevada, United States  [doi>10.1145/240518.240538]
	13	Daniel D. Gajski , Frank Vahid, Specification and Design of Embedded Hardware-Software Systems, IEEE Design & Test, v.12 n.1, p.53-67, March 1995  [doi>10.1109/54.350695]
	14	Lars Hagen, Andrew B. Kahng, Fadi L. Kurdahi, and Champaka Ramachandran. On the intrinsic Rent parameter and spectra-based partitioning methods. Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13:27-37, 1994.
	15	Lars W. Hagen , Dennis J.-H. Huang , Andrew B. Kahng, On implementation choices for iterative improvement partitioning algorithms, Proceedings of the conference on European design automation, p.144-149, September 18-22, 1995, Brighton, England
	16	Lars W. Hagen , Dennis J. H. Huang , Andrew B. Kahng, Quantified suboptimality of VLSI layout heuristics, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.216-221, June 12-16, 1995, San Francisco, California, United States  [doi>10.1145/217474.217532]
	17	S. Hauck , G. Borriello, An evaluation of bipartitioning techniques, Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95), p.383, March 27-29, 1995
	18	Scott Hauck , Gaetano Borriello, Logic partition orderings for multi-FPGA systems, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.32-38, February 12-14, 1995, Monterey, California, United States  [doi>10.1145/201310.201315]
	19	Dennis J.-H. Huang , Andrew B. Kahng, Multi-way system partitioning into a single type or multiple types of FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.140-145, February 12-14, 1995, Monterey, California, United States  [doi>10.1145/201310.201332]
	20	D. J. -H. Huang , A. B. Kahng, When clusters meet partitions: new density-based methods for circuit decomposition, Proceedings of the 1995 European conference on Design and Test, p.60, March 06-09, 1995
	21	Michael Hutton , J. P. Grossman , Jonathan Rose , Derek Corneil, Characterization and parameterized random generation of digital circuits, Proceedings of the 33rd annual conference on Design automation, p.94-99, June 03-07, 1996, Las Vegas, Nevada, United States  [doi>10.1145/240518.240537]
	22	L. James Hwang and Abbas E1Gamal. Min-cut replication in partitioned networks. Transactions on Computer-Aided Design of lntegrated Circuits and Systems, 14:96-106, 1995.
	23	I. Karkowski , R. H. J. M. Otten, An Automatic Hardware-Software Partitioner Based on the Possibilistic Programming., Proceedings of the 1996 European conference on Design and Test, p.467, March 11-14, 1996
	24	Yoshinori Katsura , Tetsushi Koide , Shin'ichi Wakabayashi , Noriyosh Yoshida, A new system partitioning method under performance and physical constraints for multi-chip modules, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.20-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan  [doi>10.1145/224818.224887]
	25	Chunghee Kim , Hyunchul Shin , Young-Uk Yu, Performance-driven circuit partitioning for prototyping by using multiple FPGA chips, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.19-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan  [doi>10.1145/224818.224886]
	26	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	27	Thomas Lengauer, Combinatorial algorithms for integrated circuit layout, John Wiley & Sons, Inc., New York, NY, 1990
	28	Jianmin Li , John Lillis , Chung-Kuan Cheng, Linear decomposition algorithm for VLSI design applications, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.223-228, November 05-09, 1995, San Jose, California, United States
	29	Jianmin Li , John Lillis , Lung-Tien Liu , Chung-Kuan Cheng, New spectral linear placement and clustering approach, Proceedings of the 33rd annual conference on Design automation, p.88-93, June 03-07, 1996, Las Vegas, Nevada, United States  [doi>10.1145/240518.240536]
	30	Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, and T.C. Hu. A replication cut for two-way partitioning. Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14:623-630, 1995.
	31	Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, and Te C. Hu. Performance-driven partitioning using a replication graph approach. In Design Automation Conference (DAC), pages 206-210. ACM/IEEE, 1995.
	32	Lung-Tien Liu , Ming-Ter Kuo , Shih-Chen Huang , Chung-Kuan Cheng, A gradient method on the initial partition of Fiduccia-Mattheyses algorithm, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.229-234, November 05-09, 1995, San Jose, California, United States
	33	Ralf Niemann , Peter Marwedel, Hardware/Software Partitioning using Integer Programming, Proceedings of the 1996 European conference on Design and Test, p.473, March 11-14, 1996
	34	Rajmohan Rajaraman and D.F. Wong. Optimum clustering for delay minimization. Transactions on Computer-Aided Design of lntegrated Circuits and Systems, 14:1490-1495, 1995.
	35	Bernhard M. Riess , Konrad Doll , Frank M. Johannes, Partitioning very large circuits using analytical placement techniques, Proceedings of the 31st annual conference on Design automation, p.646-651, June 06-10, 1994, San Diego, California, United States  [doi>10.1145/196244.196602]
	36	Bernhard M. Riess , Heiko A. Giselbrecht , Bernd Wurth, A new K-way partitioning approach for multiple types of FPGAs, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.48-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan  [doi>10.1145/224818.224915]
	37	Bernhard M. Riess and Andreas A. Schoene. A new layout design system for multichip modules. International Journal of High Speed Elecnvnics and Systems, 6:509-538, 1995.
	38	Kalapi Roy-Neogi , Carl Sechen, Multiple FPGA partitioning with performance optimization, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.146-152, February 12-14, 1995, Monterey, California, United States  [doi>10.1145/201310.201333]
	39	Youssef G. Saab, A Fast and Robust Network Bisection Algorithm, IEEE Transactions on Computers, v.44 n.7, p.903-913, July 1995  [doi>10.1109/12.392848]
	40	Prashant Sawkar , Donald Thomas, Multi-way partitioning for minimum delay for look-up table based FPGAs, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.201-210, June 12-16, 1995, San Francisco, California, United States  [doi>10.1145/217474.217530]
	41	Rolf Schlagenhaft , Martin Ruhwandl , Christian Sporrer , Herbert Bauer, Dynamic load balancing of a multi-cluster simulator on a network of workstations, Proceedings of the ninth workshop on Parallel and distributed simulation, p.175-180, June 13-16, 1995, Lake Placid, New York, United States
	42	Bernd Schürmann , Joachim Altmeyer , Gerhard Zimmermann, Three-phase chip planning — an improved top-down chip planning strategy, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.598-605, November 1992, Santa Clara, California, United States
	43	Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, Norwell, MA, 1993
	44	Minshine Shih , Ernest S. Kuh, Quadratic Boolean programming for performance-driven system partitioning, Proceedings of the 30th international conference on Design automation, p.761-765, June 14-18, 1993, Dallas, Texas, United States  [doi>10.1145/157485.165121]
	45	Minshine Shih and Ernest S. Kuh. Circuit partitioning under capacity and i/o constraints. In Custom Integrated Circuits Conference, pages 659-662. IEEE, 1994.
	46	Christian Sporrer , Herbert Bauer, Corolla partitioning for distributed logic simulation of VLSI-circuits, Proceedings of the seventh workshop on Parallel and distributed simulation, p.85-92, May 16-19, 1993, San Diego, California, United States
	47	Katsunori Tani, A robust min-cut improvement algorithm based on dynamic look-ahead weighting, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.21-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan  [doi>10.1145/224818.224888]
	48	Ren-Song Tsay and Ernest Kuh. A unified approach to partitioning and placement. Transactions on Circuits and Systems, 38:521-533, 1991.
	49	Hirendu Vaishnav , Massoud Pedram, Delay optimal partitioning targeting low power VLSI circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.638-643, November 05-09, 1995, San Jose, California, United States
	50	Hannah Honghua Yang , D. F. Wong, New algorithms for min-cut replication in partitioned circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.216-222, November 05-09, 1995, San Jose, California, United States
	51	Honghua Yang , D. F. Wong, Circuit clustering for delay minimization under area and pin constraints, Proceedings of the 1995 European conference on Design and Test, p.65, March 06-09, 1995
	52	Ching-Wei Yeh. On the acceleration of flow-oriented circuit clustering. Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14:1305-1308, 1995.
	53	Ching-Wei Yeh, Chung-Kuan Cheng, and Ting-Ting Y. Lin. Circuit clustering using a stochastic flow injection method. Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14:154-162, 1995.
	54	Ching-Wei Yeh, Chung-Kuan Cheng, and Ting-Ting Y. Lin. Optimization by iterative improvement: an experimental evaluation on two-way partitioning. Trans. on Computer-Aided Design of lntegrated Circuits and Systems, 14:145-153, 1995.

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