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Universal switch modules for FPGA design
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Source ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 1 ,  Issue 1  (January 1996) table of contents
Pages: 80 - 101  
Year of Publication: 1996
ISSN:1084-4309
Authors
Yao-Wen Chang  University of Texas at Austin
D. F. Wong  Chinese University of Hong Kong
C. K. Wong
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 10,   Downloads (12 Months): 84,   Citation Count: 30
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ABSTRACT

A switch module M with W terminals on each side is said to be universal if every set of nets satisfying the dimensional constraint (i.e., the number of nets on each side of M is at most W) is simultaneously rout able through M. In this article, we present a class of universal switch modules. Each of our switch modules has 6Wswitches and switch-module flexibility three (i.e, Fs=3). We prove that no switch module with less than 6W switches can be universal. We also compare our switch modules with those used in the Xilinx XC4000 family FPGAs and the antisymmetric switch modules (with FS=3) suggested by Rose and Brown [1991]. Although these two kinds of switch modules also have FS=3 and 6W switches, we show that they are not universal. Based on combinatorial counting techniques, we show that each of our universal switch modules can accommodate up to 25% more routing instances, compared with the XC4000-type switch module of the same size. Experimental results demonstrate that our universal switch modules improve routability at the chip level. Finally, our work also provides a theoretical insight into the important observation by Rose and Brown [1991] (based on extensive experiments) that FS=3 is often sufficient to provide high routability.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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BROWN, S., ROSE, J., AND VRANESIC, Z.G. 1993. A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Computer-Aided Des. 12, 12, 1827-1838.
 
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BROWN, S., ROSE, J., AND VRANESIC, Z.G. 1992b. A detailed router for field-programmable gate arrays. IEEE Trans. Comput.-Aided Des. 11,620-627.
 
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CHEN, C.-D., LEE, Y.-S., WU, C.-H., AND LIN, Y.-L. 1995. TRACER-fpga: a router for RAM-based FPGAs. IEEE Trans. Comput.-Aided Des. 14, 3 (March), 371-374.
 
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FUJIYOSHI, K., KAJITANI, Y., AND NIJTSU, H. 1994. Design of optimum totally perfect connection-blocks of FPGA. In Proceedings of the IEEE International Symposium on Circuits and Systems (London, May 30-June 6), 221-224.
 
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HSIEH, H. C. ET AL., 1990. Third-generation architecture boosts speed and density of field-programmable gate arrays. In Proceedings of the IEEE Custom Integrated Circuits Conference (Boston, MA, May), 31.2.1-31.2.7.
 
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LEMIEUX, G. AND BROWN, S. 1993. A detailed routing algorithm for allocating wire segments in field-programmable gate arrays. In Proceedings of the ACM/SIGDA Physical Design Workshop (Lake Arrowhead, CA), 215-226.
 
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ROSE, J. AND BROWN, S. 1991. Flexibility ofinterconnection structures for field-programmable gate arrays. IEEE J. Solid-State Circuits. 26, 3, 277-282.
 
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ROSE, J., FRANCIS, R., LEWIS, D., AND CHOW, P. 1990. Architecture of programmable gate arrays: The effect of logic block functionality on area efficiency. IEEE J. Solid-State Circuits 25, 1217-1225.
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Wu, Y.-L., TSUKIYAMA, S., AND MAREK-SADOWSKA, M. 1994. Computational complexity of 2-D FPGA routing for arbitrary switch box topologies. In Proceedings of the ACM International Workshop on FPGA (Berkeley, CA, Feb. 13-15).
 
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XILINX INC. 1994. The Programmable Logic Data Book.
 
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CITED BY  30
 
 
 
 
 
 
 
 
 
 
 


REVIEW

"Howard H. Chen : Reviewer"

A class of universal switch modules with the maximum routing capacity and minimum number of programmable switches for field programmable gate arrays (FPGAs) is identified. For novice readers, the authors provide a comprehensive overview of the  more...

Collaborative Colleagues:
Yao-Wen Chang: colleagues
D. F. Wong: colleagues
C. K. Wong: colleagues

Peer to Peer - Readers of this Article have also read: