Power minimization in IC design

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Power minimization in IC design: principles and applications

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ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 1 , Issue 1 (January 1996) table of contents

Pages: 3 - 56

Year of Publication: 1996

ISSN:1084-4309

Author

Massoud Pedram

University of Southern California

Publisher

ACM New York, NY, USA

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ABSTRACT

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

REFERENCES

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	1	ALIDINA, M., MONTEIRO, J., DEVADAS, S., GHOSH, A., AND PAPAEFTHYMIOU, M. 1994. Precomputation-based sequential logic optimization for low power. In Proceedings of the 1994 International Workshop on Low Power Design. ACM/IEEE, 57-62.
	2	AMRUTUR, B. S. AND HOROWITZ, M. 1994. Techniques to reduce power in fast wide memories. In Proceedings of the IEEE Symposium on Low Power Electronics. 92-93.
	3	William C. Athas , Lars J. Svensson , Jeffrey G. Koller , Nestoras Tzartzanis , Eric Ying-Chin Chou, Low-power digital systems based on adiabatic-switching principles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.398-407, Dec. 1994 [doi>10.1109/92.335009]
	4	ATHAS, W. 1996. Energy-recovery CMOS. In Low Power Design Methodologies. J. Rabaey and M. Pedram, Eds. Kluwer, Boston, Mass., 63-97.
	5	R. Iris Bahar , Fabio Somenzi, Boolean techniques for low power driven re-synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.428-432, November 05-09, 1995, San Jose, California, United States
	6	BAKOGLU, H. 1990. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Menlo Park, Calif.
	7	Peter A. Beerel , Cheng-Ta Hsieh , Suhrid Wadekar, Estimation of energy consumption in speed-independent control circuits, Proceedings of the 1995 international symposium on Low power design, p.39-44, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224089]
	8	Luca Benini , Giovanni De Micheli, Transformation and synthesis of FSMs for low-power gated-clock implementation, Proceedings of the 1995 international symposium on Low power design, p.21-26, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224086]
	9	BENINI, L., FAVALLI, M. AND RICCO, B. 1994. Analysis of hazard contribution to power dissipation in CMOS IC's. In Proceedings of the 1994 ACM/IEEE International Workshop on Low Power Design. 27-32.
	10	Michel R. C. M. Berkelaar , Jochen A. G. Jess, Gate sizing in MOS digital circuits with linear programming, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	11	Manjit Borah , Robert Michael Owens , Mary Jane Irwin, Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint, Proceedings of the 1995 international symposium on Low power design, p.167-172, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224111]
	12	BRAYTON, R. K., HACHTEL, G. D. AND SANGIOVANNI-VINCENTELLI, A.L. 1990. Multilevel logic synthesis. Proc. IEEE 78 (Feb.), 264-300.
	13	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	14	BRODERSEN, R. W., ET AL. 1991.Technologies for personal communications. In Proceedings of the VLSI Symposium. 5-9.
	15	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	16	Premal Buch , Shen Lin , Vijay Nagasamy , Ernest S. Kuh, Techniques for fast circuit simulation applied to power estimation of CMOS circuits, Proceedings of the 1995 international symposium on Low power design, p.135-138, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224105]
	17	Richard Burch , Farid Najm , Ping Yang , Dale Hocevar, Pattern-independent current estimation for reliability analysis of CMOS circuits, Proceedings of the 25th ACM/IEEE conference on Design automation, p.294-299, June 12-15, 1988, Atlantic City, New Jersey, United States
	18	BURCH, R., NAJM, F. N., YANG, P. AND TRICK, T. 1993. A Monte Carlo approach for power estimation. IEEE Trans. VLSI Systems 1, 1 (Mar.), 63-71.
	19	CARLEY, L. R. AND LYS, I. 1994. QuadRail: A design methodology for low power ICs. IEEE Trans. VLSI Systems 2, 4 (Dec.), 383-395.
	20	CHAKRAVARTY, S. 1989. On the complexity of using BDDs for the synthesis and analysis of Boolean circuits. In Proceedings of the 27th Annual Allerton Conference on Communication, Control and Computing. 730-739.
	21	CHANDRAKASAN, A., ALLMON, R., STRATAKOS, A. AND BRODERSEN, R. W. 1994. Design of portable systems. In Proceedings of the IEEE Custom Integrated Circuit Conference. San Diego, Calif.
	22	CHANDRAKASAN, A., SHENG, S. AND BRODERSEN, R. W. 1992a Low-power techniques for portable real-time DSP applications. In Proceedings of VLSI Design.
	23	CHANDRAKASAN, A., SHENG, S. AND BRODERSEN, R.W. 1992b. Low-power CMOS design. IEEE J. Solid-State Circuits. 472-484.
	24	Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
	25	CHAO, K. Y. AND TONG, D. F. 1994. Low-power consideration in floorplan design. In Proceedings of the 1994 International Workshop on Low Power Design. ACM/IEEE 45-50.
	26	Jui-Ming Chang , Massoud Pedram, Register allocation and binding for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.29-35, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217502]
	27	CHANG, J-M. AND PEDRAM, M. 1995b. Power efficient module allocation and binding. CENG Tech. Rep. 95-16. University of Southern California.
	28	Tan-Li Chou , Kaushik Roy , Sharat Prasad, Estimation of circuit activity considering signal correlations and simultaneous switching, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.300-303, November 06-10, 1994, San Jose, California, United States
	29	Tan-Li Chou , Kaushik Roy, Statistical estimation of sequential circuit activity, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.34-37, November 05-09, 1995, San Jose, California, United States
	30	William A. Chren, Jr., Low delay-power product CMOS design using one-hot residue coding, Proceedings of the 1995 international symposium on Low power design, p.145-150, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224107]
	31	CONG, J. AND PREAS, B. T. 1988. A new algorithm for standard cell global routing. In Proceedings of the IEEE International Conference on Computer Aided Design. 176-180.
	32	Jason Cong , Cheng-Kok Koh, Simultaneous driver and wire sizing for performance and power optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.408-425, Dec. 1994 [doi>10.1109/92.335010]
	33	CONG, J. AND KOH, C-K. 1995. Minimum-cost bounded-skew clock routing. In Proceedings of the IEEE International Symposium on Circuits and Systems. 215-218.
	34	CRITIC, M.A. 1987. Estimating dynamic power consumption of CMOS circuits. In Proceedings of the IEEE International Conference on Computer Aided Design. 534-537.
	35	DAVARI, B., DENNARD, R. H. AND SHAHIDI, G.G. 1995. CMOS scaling for high performance and low power. Proc. IEEE 83, 4 (Apr.), 408-425.
	36	DEVADAS, S., KEUTZER, K. AND WHITE, J. 1992. Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 11, 3 (Mar.), 373-383.
	37	DING, C-S. AND PEDRAM, M. 1995. Tagged probabilistic simulation provides accurate and efficient power estimates at the gate level. In Proceedings of the IEEE Symposium on Low Power Electronics. 42-43.
	38	DOBBERPUHL, D., ET AL. 1992. A 200MHz, 64b, dual issue CMOS microprocessor. Digest of Technical Paper. ISSC '92. 106-107.
	39	EAGER, J. 1992. Advances in rechargeable batteries spark product innovation. In Proceed-ings of the 1992 Silicon Valley Computer Conference. (Santa Clara, Calif.), 243-253.
	40	ERCOLANI, S., FAVALLI, M., DAMIANI, M., OLIVO, P. AND RICCO, B. 1989. Estimate of signal probability in combinational logic networks. In First European Test Conference. 132-138.
	41	Amir H. Farrahi , Gustavo E. Téllez , Majid Sarrafzadeh, Memory segmentation to exploit sleep mode operation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.36-41, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217503]
	42	M. Favalli , L. Benini, Analysis of glitch power dissipation in CMOS ICs, Proceedings of the 1995 international symposium on Low power design, p.123-128, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224103]
	43	FJELDLY, T. A. AND SHUn, M. 1993. Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFET's. IEEE Trans. Electron Devices 4, 1 (Jan.), 137-145.
	44	FURBER, S. 1995. Computing without clocks: micropipelining the ARM processor. In Asynchronous Digital Circuit Design. G. Birtwistle and A. Davis, Eds. Springer Verlag, New York, 211-262.
	45	GEORGE, B. J., GOSSAIN, D., TYLER, S. C., WLOKA, M. G. AND YEAP, G. K.H. 1994. Power analysis and characterization for semi-custom design. In Proceedings of the 1994 International Workshop on Low Power Design. 215-218.
	46	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	47	GOLDSTEIN, H. 1979. Controllability/observability of digital circuits. IEEE Trans. Circuits Syst. 26, 9 (Sep.), 685-693.
	48	Gary D. Hachtel , Mariano Hermida , Abelardo Pardo , Massimo Poncino , Fabio Somenzi, Re-encoding sequential circuits to reduce power dissipation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.70-73, November 06-10, 1994, San Jose, California, United States
	49	Gary D. Hachtel , Enrico Macii , Abelardo Pardo , Fabio Somenzi, Probabilistic analysis of large finite state machines, Proceedings of the 31st annual conference on Design automation, p.270-275, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196374]
	50	HAHM, M. 1995. Modest power savings for applications dominated by switching of large capacitive loads. In Proceedings of the 1995 IEEE Symposium on Low Power Electronics. 60-61.
	51	HEDENSTIERNA, N. AND JEPPSON, K. 1987. CMOS circuit speed and buffer optimization. IEEE Trans. Computer-Aided Des. Integrated Circuits Syst. 6, 3 (Mar.), 270-281.
	52	Anthony M. Hill , Sung-Mo Steve Kang, Determining accuracy bounds for simulation-based switching activity estimation, Proceedings of the 1995 international symposium on Low power design, p.215-220, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224119]
	53	HOROWITZ, M., INDERMAUR, T. AND GONZALEZ, R. 1995. Low-power digital design. In Proceedings of the 1995 IEEE Symposium on Low Power Electronics. 8-11.
	54	Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217579]
	55	Charlie X. Huang , Bill Zhang , An-Chang Deng , Burkhard Swirski, The design and implementation of PowerMill, Proceedings of the 1995 international symposium on Low power design, p.105-110, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224100]
	56	Sasan Iman , Massoud Pedram, Multi-level network optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.372-377, November 06-10, 1994, San Jose, California, United States
	57	Sasan Iman , Massoud Pedram, Logic extraction and factorization for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.248-253, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217537]
	58	Sasan Iman , Massoud Pedram, Two-level logic minimization for low power, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.433-438, November 05-09, 1995, San Jose, California, United States
	59	IMAN, S., TSUI, C. Y. AND PEDRAM, M. 1995. PLA minimization for low power VLSI designs. CENG Tech. Rep. 95-27, Dept. of EL-Systems, University of Southern California.
	60	ITOH, K., SASAKI, K. AND NAKAGOME, Y. 1995. Trends in low-power RAM circuit technologies. Proc. IEEE 83, 4 (Apr.), 524-543.
	61	KANG, S.M. 1986. Accurate simulation of power dissipation in VLSI circuits. IEEE J. Solid State Circuits. 21, 5 (Oct.), 889-891.
	62	KANG, S. M. AND LEBLEBICI, Y. 1996. CMOS Digital Integrated Circuits: Analysis and Design. McGraw-Hill, New York.
	63	KAPOOR, B. 1994. Improving the accuracy of circuit activity measurement. In Proceedings of the 1994 International Workshop on Low Power Design. 111-116.
	64	KERNIGHAN, B. W. AND LIN, S. 1970. An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. 49, 2 (Feb.), 291-307.
	65	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	66	KIRKPATRICK, S., GELATT, C. D. AND VECCHI, M.P. 1983. Optimization by simulated annealing. Science 220, 4598 (May), 671-680.
	67	KLEINHANS, J. M., SIGL, a., JOHANNES, F. M. AND ANTREICH, K.J. 1991. GORDIAN: VLSI placement by quadratic programming and slicing optimization. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 10, 3 (Mar.), 356-365.
	68	KOBAYASHI, T. AND SAKURAI, T. 1994. Self-adjusting threshold-voltage scheme for low voltage high speed operation. In Proceedings of CICC. 271-274.
	69	Balakrishnan Krishnamurthy , Ioannis G. Tollis, Improved Techniques for Estimating Signal Probabilities, IEEE Transactions on Computers, v.38 n.7, p.1041-1045, July 1989 [doi>10.1109/12.30854]
	70	KUDVA, P. AND AKELLA, V. 1994. A technique for estimating power in asynchronous circuits. In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems. 166-175.
	71	Nand Kumar , Srinivas Katkoori , Leo Rader , Ranga Vemuri, Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems, IEEE Design & Test, v.12 n.3, p.70-84, September 1995 [doi>10.1109/MDT.1995.466383]
	72	LANDMAN, P.E. AND RABAEY, J. 1993. Power estimation for high level synthesis. In Proceedings of the European Conference on Design Automation. 361-366.
	73	Paul E. Landman , Jan M. Rabaey, Activity-sensitive architectural power analysis for the control path, Proceedings of the 1995 international symposium on Low power design, p.93-98, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224098]
	74	Luciano Lavagno , Patrick C. McGeer , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli, Timed shared circuits: a power-efficient design style and synthesis tool, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.254-260, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217538]
	75	LAWLER, E. L., LEVITT, K. N. AND TURNER, J. 1969. Module clustering to minimize delay in digital networks. IEEE Trans. Comput. 45-57.
	76	LEE, K. W. AND SECHEN, C. 1988. A new global router for row-based layout. In Proceedings of the IEEE International Conference on Computer Aided Design. 180-183.
	77	LEISERSON, C. E., ROSE, F. M. AND SAXE, J.B. 1983. Optimizing synchronous circuitry by retiming. In Proceedings of the Third Caltech Conference on VLSI. 23-36.
	78	Christopher K. Lennard , A. Richard Newton, An estimation technique to guide low power resynthesis algorithms, Proceedings of the 1995 international symposium on Low power design, p.227-232, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224121]
	79	LIEBERSTEIN, H.M. 1968. A Course in Numerical Analysis. Harper & Row, New York.
	80	LIN, B. AND DE MAN, H. 1993. Low-power driven technology mapping under timing constraints. In Proceedings of the International Conference on Computer Design. 421-427.
	81	How-Rern Lin , Ting-Ting Hwang, Power reduction by gate sizing with path-oriented slack calculation, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.2-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224827]
	82	Jiing-Yuan Lin , Tai-Chien Liu , Wen-Zen Shen, A cell-based power estimation in CMOS combinational circuits, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.304-309, November 06-10, 1994, San Jose, California, United States
	83	LIN, B., AND NEWTON, A.R. 1989. Synthesis of multiple-level logic from symbolic high-level description languages. In Proceedings of IFIP International Conference on Very Large-Scale Integration. 187-196.
	84	MALINIAK, D. 1992. Better batteries for low-power jobs. Electron. Des. 40, 15 (July), 18.
	85	Srilatha Manne , Abelardo Pardo , R. Iris Bahar , Gary D. Hachtel , Fabio Somenzi , Enrico Macii , Massimo Poncino, Computing the maximum power cycles of a sequential circuit, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.23-28, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217501]
	86	Radu Marculescu , Diana Marculescu , Massoud Pedram, Switching activity analysis considering spatiotemporal correlations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.294-299, November 06-10, 1994, San Jose, California, United States
	87	Radu Marculescu , Diana Marculescu , Massoud Pedram, Efficient power estimation for highly correlated input streams, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.628-634, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217601]
	88	Diana Marculescu , Radu Marculescu , Massoud Pedram, Information theoretic measures of energy consumption at register transfer level, Proceedings of the 1995 international symposium on Low power design, p.81-86, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224096]
	89	Raul San Martin , John P. Knight, Power-profiler: optimizing ASICs power consumption at the behavioral level, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.42-47, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217504]
	90	MEHRA, R., LIDSKY, D. B., ABNOUS, A., LANDMAN, P. E., AND RABAEY, J.M. 1996. Algorithm and architectural level methodologies for low power. In Low Power Design Methodologies. J. Rabaey and M. Pedram, Eds. Kluwer, New York, 333-362.
	91	MEHRA, R., AND RABAEY, J. 1994. Behavioral level power estimation and exploration. In Proceedings of the 1994 International Workshop on Low Power Design. 197-202.
	92	Huzefa Mehta , Manjit Borah , Robert Michael Owens , Mary Jane Irwin, Accurate estimation of combinational circuit activity, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.618-622, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217599]
	93	Noel Menezes , Ross Baldick , Lawrence T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.144-151, November 05-09, 1995, San Jose, California, United States
	94	MENG, T. H., GORDON, B. M., TSERN, E. K., AND HUNG, C. 1995. Portable video-on-demand in wireless communication. Proc. IEEE 83, 4 (April), 659-680.
	95	José Monteiro , Srinivas Devadas , Abhijit Ghosh, Retiming sequential circuits for low power, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.398-402, November 07-11, 1993, Santa Clara, California, United States
	96	José Monteiro , Srinivas Devadas , Bill Lin, A methodology for efficient estimation of switching activity in sequential logic circuits, Proceedings of the 31st annual conference on Design automation, p.12-17, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196252]
	97	J. Monteiro , J. Rinderknecht , S. Devadas , A. Ghosh, Optimization of combinational and sequential logic circuits for low power using precomputation, Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95), p.430, March 27-29, 1995
	98	MURGAI, R., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. 1994. Decomposition of logic functions for minimum transition activity. In Proceedings of the 1994 International Workshop on Low Power Design. 33-38.
	99	NAJM, F. N., BURCH, R., YANG, P., AND HAJJ, L. 1990. Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 9, 4 (Apr.), 439-450.
	100	NAJM, F.N. 1993. Transition density: A new measure of activity in digital circuits. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 12, 2 (Feb.), 310-323.
	101	NAJM, F.N. 1994. Low pass filter for computing transition density in digital circuits. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 13, 9 (Sep.), 1123-1131.
	102	Farid N. Najm, Towards a high-level power estimation capability, Proceedings of the 1995 international symposium on Low power design, p.87-92, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224097]
	103	Farid N. Najm , Shashank Goel , Ibrahim N. Hajj, Power estimation in sequential circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.635-640, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217602]
	104	Lars S. Nielsen , Cees Niessen, Low-power operation using self-timed circuits and adaptive scaling of the supply voltage, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.391-397, Dec. 1994 [doi>10.1109/92.335008]
	105	OLSON, E., AND KANG, S. 1994. Low-power state assignment for finite state machines. In Proceedings of the 1994 International Workshop on Low Power Design. 63-68.
	106	PARKER, K. P., AND MCCLUSKEY, g. 1975. Probabilistic treatment of general combinational networks. IEEE Trans. Comput. 24, 6 (June), 668-670.
	107	PEDRAM, M., AND PREAS, B.T. 1989. Interconnection length estimation for optimized standard cell layouts. In Proceedings of the IEEE International Conference on Computer Aided Design. 390-393.
	108	PEDRAM, M., MAREK-SADOWSKA, M., AND KUH, E. S. 1990. Floorplanning with pin assignment. In Proceedings of the IEEE International Conference on Computer Aided Design. 98-101.
	109	Massoud Pedram , Narasimha Bhat, Layout driven technology mapping, Proceedings of the 28th conference on ACM/IEEE design automation, p.99-105, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127635]
	110	PEDRAM, M. 1994. Power estimation and optimization at the logic level. Int. J. High Speed Electron. Syst. 5, 2 (June), 179-202.
	111	POWELL, S. R., AND CHAU, P.M. 1995. A model for estimating power dissipation in a class of DSP VLSI chips. IEEE Trans. Circuits Syst. 36, 6 (June), 646-650.
	112	POWERS, R.A. 1995. Batteries for low power electronics. Proc. IEEE 38, 4 (Apr.), 687-693.
	113	PRASAD, S. C., AND ROY, K. 1994. Circuit optimization for minimization of power consumption under delay constraint. In Proceedings of the 1994 International Workshop on Low Power Design. 15-20.
	114	QUARLES, T. 1989. The SPICE3 implementation guide. Tech. Rep. M89-44, Electronics Research Laboratory, Univ. of California, Berkeley, Calif.
	115	RABAEY, J., AND PEDRAM, M. EDS. 1996. Low Power Design Methodologies. Kluwer, New York.
	116	Salil Raje , Majid Sarrafzadeh, Variable voltage scheduling, Proceedings of the 1995 international symposium on Low power design, p.9-14, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224084]
	117	RAJGOPAL, S., AND MEHTA, a. 1994. Experiences with simulation-based schematic level current estimation. In Proceedings of the 1994 International Workshop on Low Power Design. 9-14.
	118	RAJSKI, J., AND VASUDEVAMURTHY, J. 1993. The testability-preserving concurrent decomposition and factorization of Boolean expressions. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 11, 6 (June), 778-793.
	119	Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
	120	RAGHUNATHAN, A., AND JHA, N. K. 1995a. An ILP formulation for low power based on minimizing switched capacitance during datapath allocation. In Proceedings of the IEEE International Symposium on Circuits and Systems.
	121	Anand Raghunathan , Niraj K. Jha, An iterative improvement algorithm for low power data path synthesis, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.597-602, November 05-09, 1995, San Jose, California, United States
	122	ROBERTS, K.n. 1984. Automatic layout in the Highland system. In Proceedings of the IEEE International Conference on Computer Aided Design. 224-226.
	123	RoY, K., AND PRASAD, S. C. 1993. Circuit activity based logic synthesis for low power reliable operations. IEEE Trans. VLSI Syst. 1, 4 (Dec.), 503-513.
	124	A. Salz , M. Horowitz, IRSIM: an incremental MOS switch-level simulator, Proceedings of the 26th ACM/IEEE conference on Design automation, p.173-178, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74412]
	125	SAVIR, J., DITLOW, G., AND BARDELL, P. 1984. Random pattern testability. IEEE Trans. Comput. 33, 1 (Jan.), 1041-1045.
	126	SAVOJ, H., BRAYTON, R. K., AND TOUATI, H.J. 1991. Extracting local don't cares for network optimization. In Proceedings of the IEEE International Conference on Computer Aided Design. 514-517.
	127	SCHNEIDER, P., AND SCHLICHTMANN, U. 1994. Decomposition of Boolean functions for low power based on a new power estimation technique. In Proceedings of the 1994 International Workshop on Low Power Design. 123-128.
	128	Sharad C. Seth , Vishwani D. Agrawal, A new model for computation of probabilistic testability in combinational circuits, Integration, the VLSI Journal, v.7 n.1, p.49-75, April 1989 [doi>10.1016/0167-9260(89)90059-X]
	129	SETH, S. C., PAN, L., AND AGRAWAL, V. D. 1985. PREDICT--Probabilistic estimation of digital circuit testability. In Proceedings of the Fault Tolerant Computing Symposium. 220 -225.
	130	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	131	Wen-Zen Shen , Jiing-Yuan Lin , Fong-Wen Wang, Transistor reordering rules for power reduction in CMOS gates, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.1-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224825]
	132	SMALL, C. 1994. Shrinking devices put the squeeze on system packaging. EDN 39, 4 (Feb.), 41-46.
	133	SWAN, M., AND BURLESON, W. 1994. Limited-weight codes for low power I/O. In Proceedings of the 1994 International Workshop on Low-Power Design. 209-214.
	134	STRATAKOS, A., BRODERSEN, R. W., AND SANDERS, S. R. 1994. High-efficiency low-voltage DC-DC conversion for portable applications. In Proceedings of the 1994 International Workshop on Low-Power Design. 105-110.
	135	Su, C-L., TsuI, C-Y., AND DESPAIN, A.M. 1994. Low power architecture design and compilation techniques for high-performance processors. In COMPCON '94 Digest of Technical Papers. 489-498.
	136	SVENSSON, C., AND LIU, D. 1994. A power estimation tool and prospects of power savings in CMOS VLSI chips. In Proceedings of the 1994 International Workshop on Low-Power Design. 171-176.
	137	SVENSSON, C., AND LIU, D. 1996. Low power circuit techniques. In Low Power Design Methodologies. J. Rabaey and M. Pedram, Eds. Kluwer, New York, 38-64.
	138	Yutaka Tamiya , Yusuke Matsunaga , Masahiro Fujita, LP based cell selection with constraints of timing, area, and power consumption, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.378-381, November 06-10, 1994, San Jose, California, United States
	139	TAN, C-H., AND ALLEN, J. 1994. Minimization of power in VLSI circuits using transistor sizing, input ordering and statistical power estimation. In Proceedings of the 1994 International Workshop on Low-Power Design. 75-80.
	140	Gustavo E. Téllez , Amir Farrahi , Majid Sarrafzadeh, Activity-driven clock design for low power circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.62-65, November 05-09, 1995, San Jose, California, United States
	141	Vivek Tiwari , Pranav Ashar , Sharad Malik, Technology mapping for lower power, Proceedings of the 30th international conference on Design automation, p.74-79, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164581]
	142	Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
	143	Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224120]
	144	Ren-Song Tsay , Ernest S. Kuh , Chi-Ping Hsu, Proud: a fast sea-of-gates placement algorithm, Proceedings of the 25th ACM/IEEE conference on Design automation, p.318-323, June 12-15, 1988, Atlantic City, New Jersey, United States
	145	TSAY, R.S. 1993. An exact zero-skew clock routing algorithm. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 12, 3 (Mar.), 242-249.
	146	TsuI, C-Y. 1994. Power analysis and optimization for CMOS circuits. Ph.D. Dissertation. Dept. of Computer Engineering, Univ. of Southern California.
	147	Chi-Ying Tsui , José Monteiro , Massoud Pedram , Srinivas Devadas , Alvin M. Despain , Bill Lin, Power estimation methods for sequential logic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.3, p.404-416, Sept. 1995 [doi>10.1109/92.406998]
	148	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
	149	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164577]
	150	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Exact and approximate methods for calculating signal and transition probabilities in FSMs, Proceedings of the 31st annual conference on Design automation, p.18-23, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196255]
	151	TsuI, C-Y., PEDRAM, M., AND DESPAIN, A.M. 1994b. Power efficient technology decomposition and mapping under an extended power consumption model. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 13, 9 (Sep.).
	152	Chi-Ying Tsui , Massoud Pedram , Chih-Ang Chen , Alvin M. Despain, Low power state assignment targeting two-and multi-level logic implementations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.82-87, November 06-10, 1994, San Jose, California, United States
	153	TYAGI, A. 1987. Hercules: A power analyzer of MOS VLSI circuits. In Proceedings of the IEEE International Conference on Computer Aided Design. 530-533.
	154	S. Turgis , N. Azemard , D. Auvergne, Explicit evaluation of short circuit power dissipation for CMOS logic structures, Proceedings of the 1995 international symposium on Low power design, p.129-134, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224104]
	155	Taku Uchino , Fumihiro Minami , Takashi Mitsuhashi , Nobuyuki Goto, Switching activity analysis using Boolean approximation method, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.20-25, November 05-09, 1995, San Jose, California, United States
	156	VAN BERKEL, C.H. (KEES), BURGESS, R., KESSELS, J., PEETERS, A., RONCKEN, M. AND SAEIJS, F. 1994. A fully-asynchronous low-power error corrector for the digital compact cassette player. In Proceedings of the IEEE International Solid-State Circuits Conference.
	157	VAISHNAV, g., AND PEDRAM, M. 1993. PCUBE: A performance driven placement algorithm for low power designs. In Proceedings of the European Design Automation Conference. 72-77.
	158	Hirendu Vaishnav , Massoud Pedram, Delay optimal partitioning targeting low power VLSI circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.638-643, November 05-09, 1995, San Jose, California, United States
	159	Hirendu Vaishnav, Optimization of post-layout area, delay and power dissipation, University of Southern California, Los Angeles, CA, 1996
	160	VAN OOSTENDE, P., SIX, P., AND VANDEWALLE, J., AND DE MAN, H. 1993. Estimation of typical power of synchronous {CMOS} circuits using a hierarchy of simulators. IEEE J. Solid State Circuits 28, 1 (Jan.), 26-39.
	161	VEENDRICK, H. J.M. 1984. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE J. Solid State Circuits 19 (Aug.), 468-473.
	162	VILLA, T., AND SANGIOVANNI-VINCENTELLI, A. 1990. NOVA: State assignment of finite state machines for optimal two-level logic implementations. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 9 (Sep.), 905-924.
	163	Ashok Vittal , Malgorzata Marek-Sadowska, Power optimal buffered clock tree design, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.497-502, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217577]
	164	Ashok Vittal , Malgorzata Marek-Sadowska, Power distribution topology design, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.503-507, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217578]
	165	VRUDHULA, S. B. K., AND XIE, H-Y. 1994. Techniques for CMOS power estimation and logic synthesis for low power. In Proceedings of the 1994 International Workshop on Low Power Design. 21-26.
	166	WUYTACK, S., CATTHOOR, F., FRANSSEN, F., NACHTERGAELE, L., AND DE MAN, H. 1994. Global communication and memory optimizing transformations for low power systems. In Proceedings of the 1994 International Workshop on Low Power Design. 203-208.
	167	Michael G. Xakellis , Farid N. Najm, Statistical estimation of the switching activity in digital circuits, Proceedings of the 31st annual conference on Design automation, p.728-733, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196628]
	168	Joe G. Xi , Wayne W. M. Dai, Buffer insertion and sizing under process variations for low power clock distribution, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.491-496, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217576]
	169	Gerhard Zimmerman, A new area and shape function estimation technique for VLSI layouts, Proceedings of the 25th ACM/IEEE conference on Design automation, p.60-65, June 12-15, 1988, Atlantic City, New Jersey, United States
	170	ZHOU, D., AND LIU, X. Y. 1996. Optimal drivers for high speed low power ICs. Int. J. High-Speed Electron Syst. (to appear).
	171	Qing Zhu , Wayne W.-M. Dai , Joe G. Xi, Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.628-633, November 07-11, 1993, Santa Clara, California, United States

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	John R. Sacha , Mary Jane Irwin, The logarithmic number system for strength reduction in adaptive filtering, Proceedings of the 1998 international symposium on Low power electronics and design, p.256-261, August 10-12, 1998, Monterey, California, United States
	P. Vuillod , L. Benini , G. De Micheli, Re-mapping for low power under tight timing constraints, Proceedings of the 1997 international symposium on Low power electronics and design, p.287-292, August 18-20, 1997, Monterey, California, United States
	Diana Marculescu , Radu Marculescu , Massoud Pedram, Stochastic sequential machine synthesis targeting constrained sequence generation, Proceedings of the 33rd annual conference on Design automation, p.696-701, June 03-07, 1996, Las Vegas, Nevada, United States
	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.28-32, November 09-13, 1997, San Jose, California, United States
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	D. Gizopoulos , N. Kranitis , A. Paschalis , M. Psarakis , Y. Zorian, Effective low power BIST for datapaths (poster paper), Proceedings of the conference on Design, automation and test in Europe, p.757, March 27-30, 2000, Paris, France
	A. P. Kakarountas , H. Michail , V. Kokkinos , V. Spiliotopoulos , S. Nikolaidis , C. A. Goutis, High-level safety mechanisms for safety-critical application-specific low power devices, Proceedings of the 9th WSEAS International Conference on Computers, p.1-5, July 14-16, 2005, Athens, Greece
	Masanori Muroyama , Akihiko Hyodo , Hiroto Yasuura , Tohru Ishihara, A Power Minimization Technique for Arithmetic Circuits by Cell Selection, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.268, January 07-11, 2002
	Massoud Pedram , Xunwei Wu, Analysis of power-clocked CMOS with application to the design of energy-recovery circuits, Proceedings of the 2000 conference on Asia South Pacific design automation, p.339-344, January 2000, Yokohama, Japan
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Glitch analysis and reduction in register transfer level power optimization, Proceedings of the 33rd annual conference on Design automation, p.331-336, June 03-07, 1996, Las Vegas, Nevada, United States
	P. Kh. Latypov, Energy Saving Testing of Circuits, Automation and Remote Control, v.62 n.4, p.653-655, April 2001
	Wei-Chung Cheng , Massoud Pedram, Power-optimal encoding for a DRAM address bus, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.109-118, April 2002
	Nicola Nicolici , Bashir M. Al-Hashimi, Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits, IEEE Transactions on Computers, v.51 n.6, p.721-734, June 2002
	Ki-Seok Chung , Taewhan Kim , C. L. Liu, G-vector: A New Model for Glitch Analysis in Logic Circuits, Journal of VLSI Signal Processing Systems, v.27 n.3, p.235-251, March 1, 2001
	Anand Paul , A. Ebenezer Jeyakumar , P. N. Neelakantan , K. John Pratheep, Energy recovery strategy for low power CMOS circuits design, Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing, p.1-5, December 07-09, 2003, Singapore
	Wei-Chung Cheng , Massoud Pedram, Power-optimal encoding for DRAM address bus (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.250-252, July 25-27, 2000, Rapallo, Italy
	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Fast high-level power estimation for control-flow intensive design, Proceedings of the 1998 international symposium on Low power electronics and design, p.299-304, August 10-12, 1998, Monterey, California, United States
	Behnam Amelifard , Massoud Pedram, Design of an efficient power delivery network in an soc to enable dynamic power management, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Qi Wang , Sumit Roy, RTL Power Optimization with Gate-Level Accuracy, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.39, November 09-13, 2003
	Puneet Gupta , Andrew B. Kahng , Swamy Muddu, Quantifying Error in Dynamic Power Estimation of CMOS Circuits, Analog Integrated Circuits and Signal Processing, v.42 n.3, p.253-264, March 2005
	Venkatesan Muthukumar , Bharath Radhakrishnan , Henry Selvaraj, Multiple voltage and frequency scheduling for power minimization, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.6-7, p.382-394, June-July 2005
	Hai Zhou , D. F. Wong, Optimal low powerX OR gate decomposition, Proceedings of the 37th conference on Design automation, p.104-107, June 05-09, 2000, Los Angeles, California, United States
	Hai Zhou , D. F. Wong, An exact gate decomposition algorithm for low-power technology mapping, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.575-580, November 09-13, 1997, San Jose, California, United States
	Takeshi Sakamoto , Takashi Yamada , Mamoru Mukuno , Yoshifumi Matsushita , Yasoo Harada , Hiroto Yasuura, Power analysis techniques for SoC with improved wiring models, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Nicola Nicolici , Bashir M. Al-Hashimi, Power-Conscious Test Synthesis and Scheduling, IEEE Design & Test, v.20 n.04, p.48-55, January 2003
	Dinesh Ramanathan , Rajesh Gupta, System level online power management algorithms, Proceedings of the conference on Design, automation and test in Europe, p.606-611, March 27-30, 2000, Paris, France
	M. Y. L. Wisniewski , E. Yashchin , R. L. Franch , D. P. Conrady , G. Fiorenza , I. C. Noyan, Estimating the efficiency of collaborative problem-solving, with applications to chip design, IBM Journal of Research and Development, v.47 n.1, p.77-88, January 2003
	Chris C. N. Chu , D. F. Wong, A matrix synthesis approach to thermal placement, Proceedings of the 1997 international symposium on Physical design, p.163-168, April 14-16, 1997, Napa Valley, California, United States
	Ali Iranli , Peyman Rezvani , Massoud Pedram, Low power synthesis of finite state machines with mixed D and T flip-flops, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Dinesh Ramanathan , Sandy Irani , Rajesh Gupta, Latency effects of system level power management algorithms, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	M. Münch , B. Wurth , R. Mehra , J. Sproch , N. Wehn, Automating RT-level operand isolation to minimize power consumption in datapaths, Proceedings of the conference on Design, automation and test in Europe, p.624-633, March 27-30, 2000, Paris, France
	Massoud Pedram , Qing Wu, Design considerations for battery-powered electronics, Proceedings of the 36th ACM/IEEE conference on Design automation, p.861-866, June 21-25, 1999, New Orleans, Louisiana, United States
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, High-level macro-modeling and estimation techniques for switching activity and power consumption, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.538-557, August 2003
	Bo Fu , Qiaoyan Yu , Paul Ampadu, Energy-delay minimization in nanoscale domino logic, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Eun-Gu Jung , Jeong-Gun Lee , Kyoung-Son Jhang , Jeong-A Lee , Dongsoo Har, Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions, Journal of VLSI Signal Processing Systems, v.46 n.2-3, p.133-151, March 2007
	Qing Wu , Qinru Qiu , Massoud Pedram, An interleaved dual-battery power supply for battery-operated electronics, Proceedings of the 2000 conference on Asia South Pacific design automation, p.387-390, January 2000, Yokohama, Japan
	Yann-Rue Lin , Cheng-Tsung Hwang , Allen C.-H. Wu, Scheduling techniques for variable voltage low power designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.81-97, April 1997
	Azadeh Davoodi , Ankur Srivastava, Voltage scheduling under unpredictabilities: a risk management paradigm, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.354-368, April 2005
	Vinay Devadas , Hakan Aydin, On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications, Proceedings of the 7th ACM international conference on Embedded software, October 19-24, 2008, Atlanta, GA, USA
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	I. A. Murashko , V. N. Yarmolik, Pseudorandom Test Pattern Generators for Built-in Self-Testing: A Power Reduction Method, Automation and Remote Control, v.65 n.8, p.1265-1275, August 2004
	Qinru Qiu , Qing Wu , Daniel Burns , Douglas Holzhauer, Lifetime aware resource management for sensor network using distributed genetic algorithm, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Mahesh Mamidipaka , Dan Hirschberg , Nikil Dutt, Low power address encoding using self-organizing lists, Proceedings of the 2001 international symposium on Low power electronics and design, p.188-193, August 2001, Huntington Beach, California, United States
	Wei-Chung Cheng , Massoud Pedram, Low power techniques for address encoding and memory allocation, Proceedings of the 2001 conference on Asia South Pacific design automation, p.245-250, January 2001, Yokohama, Japan
	Feng Gao , John P. Hayes, ILP-based optimization of sequential circuits for low power, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Routing methodology for minimizing 1nterconnect energy dissipation, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Mahesh N. Mamidipaka , Daniel S. Hirschberg , Nikil D. Dutt, Adaptive low-power address encoding techniques using self-organizing lists, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.827-834, October 2003
	A. Doboli, Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints, Proceedings of the conference on Design, automation and test in Europe, p.612-619, March 2001, Munich, Germany
	L. Benini , G. De Micheli , A. Lioy , E. Macii , G. Odasso , M. Poncino, Computational kernels and their application to sequential power optimization, Proceedings of the 35th annual conference on Design automation, p.764-769, June 15-19, 1998, San Francisco, California, United States
	Ki-Seok Chung , C. L. Liu, Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction, Proceedings of the 1998 international symposium on Low power electronics and design, p.215-220, August 10-12, 1998, Monterey, California, United States
	Sudarshan Banerjee , Nikil Dutt, FIFO power optimization for on-chip networks, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Ilya Obridko , Ran Ginosar, Minimal energy asynchronous dynamic adders, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.9, p.1043-1047, September 2006
	Priyadarshan Patra , Unni Narayanan, Automated phase assignment for the synthesis of low power domino circuits, Proceedings of the 36th ACM/IEEE conference on Design automation, p.379-384, June 21-25, 1999, New Orleans, Louisiana, United States
	Chi-Hong Hwang , Allen C.-H. Wu, A predictive system shutdown method for energy saving of event-driven computation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.226-241, April 2000
	Mahesh Mamidipaka , Nikil Dutt, On-chip Stack Based Memory Organization for Low Power Embedded Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.11082, March 03-07, 2003
	Steve Haga , Natasha Reeves , Rajeev Barua , Diana Marculescu, Dynamic Functional Unit Assignment for Low Power, Proceedings of the conference on Design, Automation and Test in Europe, p.11052, March 03-07, 2003
	Diana Marculescu , Radu Marculescu , Massoud Pedram, Stochastic sequential machine synthesis with application to constrained sequence generation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.658-681, July 2000
	Sasan Iman , Massoud Pedram, POSE: power optimization and synthesis environment, Proceedings of the 33rd annual conference on Design automation, p.21-26, June 03-07, 1996, Las Vegas, Nevada, United States
	Tiffany M. Mintz , James P. Davis, Low-power tradeoffs for mobile computing applications: embedded processors versus custom computing kernels, Proceedings of the 45th annual southeast regional conference, March 23-24, 2007, Winston-Salem, North Carolina
	Assim Sagahyroon , Fadi A. Aloul, Using SAT-based techniques in power estimation, Microelectronics Journal, v.38 n.6-7, p.706-715, June, 2007
	Ki-Wook Kim , Taewhan Kim , Ting-Ting Hwang , Sung-Mo Kang , C. L. Liu, Logic transformation for low-power synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.265-283, April 2002
	Jun Cheng Chi , Hung Hsie Lee , Sung Han Tsai , Mely Chen Chi, Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.6, p.637-648, June 2007
	Steve Haga , Natasha Reeves , Rajeev Barua , Diana Marculescu, Dynamic functional unit assignment for low power, The Journal of Supercomputing, v.31 n.1, p.47-62, January 2005
	Michael J. Alexander, Power optimization for FPGA look-up tables, Proceedings of the 1997 international symposium on Physical design, p.156-162, April 14-16, 1997, Napa Valley, California, United States
	Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Reduction of coupling effects by optimizing the 3-D configuration of the routing grid, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.951-954, October 2003
	Huy T. Nguyen , Abhijit Chatterjee , Rabindra K. Roy, Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis, Journal of VLSI Signal Processing Systems, v.18 n.1, p.25-38, Jan. 1998
	Chang-woo Kang , Massoud Pedram, Technology mapping for low leakage power and high speed with hot-carrier effect consideration, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Ashoka Sathanur , Antonio Pullini , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Timing-driven row-based power gating, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Hanif Fatemi , Behnam Amelifar , Massoud Pedram, Power optimal MTCMOS repeater insertion for global buses, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	K. Keutzer , O. Coudert , R. Haddad, What is the state of the art in commercial EDA tools for low power?, Proceedings of the 1996 international symposium on Low power electronics and design, p.181-187, August 12-14, 1996, Monterey, California, United States
	Yumin Zhang , Xiaobo (Sharon) Hu , Danny Z. Chen, Efficient global register allocation for minimizing energy consumption, ACM SIGPLAN Notices, v.37 n.4, April 2002
	Nicola Nicolici , Bashir M. Al-Hashimi, Testability Trade-Offs for BIST Data Paths, Journal of Electronic Testing: Theory and Applications, v.20 n.2, p.169-179, April 2004
	Yannick Bonhomme , Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel, A Gated Clock Scheme for Low Power Testing of Logic Cores, Journal of Electronic Testing: Theory and Applications, v.22 n.1, p.89-99, February 2006
	Kshirasagar Naik , David S. L. Wei, Software implementation strategies for power-conscious systems, Mobile Networks and Applications, v.6 n.3, p.291-305, June 2001
	Saraju P. Mohanty , N. Ranganathan, Energy-efficient datapath scheduling using multiple voltages and dynamic clocking, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.330-353, April 2005
	Rami Melhem , Nevine AbouGhazaleh , Hakan Aydin , Daniel Mossé, Power management points in power-aware real-time systems, Power aware computing, Kluwer Academic Publishers, Norwell, MA, 2002
	Haisang Wu , Binoy Ravindran , E. Douglas Jensen , Peng Li, Energy-efficient, utility accrual scheduling under resource constraints for mobile embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.3, p.513-542, August 2006
	Hiroyuki Okamura , Tadashi Dohi , Shunji Osaki, Performance analysis of a transaction based software system with shutdown, Proceedings of the 2nd international workshop on Software and performance, p.168-179, September 2000, Ottawa, Ontario, Canada
	Rami Melhem , Daniel Mossé , Elmootazbellah (Mootaz) Elnozahy, The Interplay of Power Management and Fault Recovery in Real-Time Systems, IEEE Transactions on Computers, v.53 n.2, p.217-231, February 2004
	Marcus T. Schmitz , Bashir M. Al-Hashimi , Petru Eles, Iterative schedule optimization for voltage scalable distributed embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.1, p.182-217, February 2004
	Sung-Mo Kang, Elements of low power design for integrated systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Luca Benini , Giovanni De Micheli, Logic synthesis for low power, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	Youn-Long Lin, Recent developments in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.1, p.2-21, Jan. 1997
	Stephen P. Boyd , Seung-Jean Kim , Dinesh D. Patil , Mark A. Horowitz, Digital Circuit Optimization via Geometric Programming, Operations Research, v.53 n.6, p.899-932, November-December 2005
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000