| Rectangle-packing-based module placement |
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International Conference on Computer Aided Design
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Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California, United States
Pages: 472 - 479
Year of Publication: 1995
ISBN:0-8186-7213-7
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Authors
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Hiroshi Murata
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School of Information Science, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa 923-12, Japan
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Kunihiro Fujiyoshi
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School of Information Science, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa 923-12, Japan
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Shigetoshi Nakatake
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School of Information Science, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa 923-12, Japan
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Yoji Kajitani
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Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Meguro-ku, Tokyo 152, Japan
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IEEE Computer Society
Washington, DC, USA
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Downloads (6 Weeks): 7, Downloads (12 Months): 101, Citation Count: 100
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ABSTRACT
The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary size, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two- dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 100
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H. Murata , K. Fujiyoshi , M. Kaneko, VLSI/PCB placement with obstacles based on sequence-pair, Proceedings of the 1997 international symposium on Physical design, p.26-31, April 14-16, 1997, Napa Valley, California, United States
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Hung-Ming Chen , Hai Zhou , F. Y. YOung , D. F. Wong , Hannah H. Yang , Naveed Sherwani, Integrated floorplanning and interconnect planning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.354-357, November 07-11, 1999, San Jose, California, United States
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Sheqin Dong , Xianlong Hong , Youliang Wu , Yizhou Lin , Jun Gu, VLSI block placement using less flexibility first principles, Proceedings of the 2001 conference on Asia South Pacific design automation, p.601-604, January 2001, Yokohama, Japan
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Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Takashi Nojima , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani, A device-level placement with multi-directional convex clustering, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
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I-Min Liu , Hung-Ming Chen , Tan-Li Chou , Adnan Aziz , D. F. Wong, Integrated power supply planning and floorplanning, Proceedings of the 2001 conference on Asia South Pacific design automation, p.589-594, January 2001, Yokohama, Japan
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Yun-Chih Chang , Yao-Wen Chang , Guang-Ming Wu , Shu-Wei Wu, B*-Trees: a new representation for non-slicing floorplans, Proceedings of the 37th conference on Design automation, p.458-463, June 05-09, 2000, Los Angeles, California, United States
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Keishi Sakanushi , Shigetoshi Nakatake , Yoji Kajitani, The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.267-274, November 08-12, 1998, San Jose, California, United States
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Hung-Ming Chen , D. F. Wong , Wai-Kei Mak , Hannah H. Yang, Faster and more accurate wiring evaluation in interconnect-centric floorplanning, Proceedings of the 11th Great Lakes symposium on VLSI, p.62-67, March 2001, West Lafayette, Indiana, United States
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Jason Cong , Tianming Kong , Faming Liang , Jun S. Liu , Wing Hung Wong , Dongmin Xu, Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application, Proceedings of the 2000 conference on Asia South Pacific design automation, p.277-282, January 2000, Yokohama, Japan
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Akira Nagao , Takashi Kambe , Isao Shirakawa, A layout approach to monolithic microwave IC, Proceedings of the 1998 international symposium on Physical design, p.65-72, April 06-08, 1998, Monterey, California, United States
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