ACM Home Page
Please provide us with feedback. Feedback
High-density reachability analysis
Full text Publisher SitePublisher Site PdfPdf (221 KB)
Source International Conference on Computer Aided Design archive
Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 154 - 158  
Year of Publication: 1995
ISBN:0-8186-7213-7
Authors
Kavita Ravi  Dept. of Electrical and Computer Engineering, University of Colorado at Boulder
Fabio Somenzi  Dept. of Electrical and Computer Engineering, University of Colorado at Boulder
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 14,   Citation Count: 43
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  

ABSTRACT

We address the problem of reachability analysis for large finite state systems. Symbolic techniques have revolutionized reachability analysis but still have limitations in traversing large systems. We present techniques to improve the symbolic breadth-first traversal and compute a lower bound on the reachable states. We identify the problem as one of density during traversal and our techniques seek to improve the same. Our results show a marked improvement on the existing breadth-first traversal methods.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
O. Coudert, C. Berthet, and J. C. Madre, "Verification of sequential machines using boolean functional vectors," in Proc. IFIP International Workshop on Applied Formal Methods for Correct VLSI Design (L. Claesen, ed.), (Leuven, Belgium), pp. 111-128, Nov. 1989.
 
2
J.R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill, "Symbolic model checking for sequential circuit verification," IEEE Transactions on Computer-Aided Design, vol. 13, pp. 401-424, Apr. 1994.
 
3
H. Cho, G. D. Hachtel, S.-W. Jeong, B. Plessier, E. Schwarz, and F. Somenzi, "ATPG aspects of FSM verification," in Proc. ICCAD, pp. 134-137, Nov. 1990.
 
4
S.-W. Jeong, B. Plessier, G. D. Hachtel, and F. Somenzi, "Variable ordering and selection for FSM traversal," in Proc. ICCAD , (Santa Clara, CA), pp. 476-479, Nov. 1991.
5
 
6
 
7
 
8
A. Ghosh and S. Devadas, "A mixed depth-first/breadth-first technique for sequential logic verification," in IWLS , (MCNC, Research Triangle Park, NC), May 1991.
 
9
10
 
11
 
12
J. Jain, J. Bitner, D. S. Fussell, and J. A. Abraham, "Functional partitioning for verification and related problems," in Brown/MIT VLSI Conference, Mar. 1992.
 
13
H. Cho, G. D. Hachtel, E. Macii, M. Poncino, K. Ravi, and F. Somenzi, "Approximate finite state machine traversal: Extensions and new results." Presented at IWLS95, Lake Tahoe, CA., May 1995.

CITED BY  43
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Collaborative Colleagues:
Kavita Ravi: colleagues
Fabio Somenzi: colleagues

Peer to Peer - Readers of this Article have also read: