Explicit evaluation of short circuit power dissipation for CMOS logic structures

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Explicit evaluation of short circuit power dissipation for CMOS logic structures

Full text

Pdf (79 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 129 - 134

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

S. Turgis	Laboratoire d'Informatique, de Robotique et de, Microélectronique deMontpellier, LIRMM UMR CNRS 9928, University Montpellier II, 161 Rue ADA, 34392 Montpellier, France
N. Azemard	Laboratoire d'Informatique, de Robotique et de, Microélectronique deMontpellier, LIRMM UMR CNRS 9928, University Montpellier II, 161 Rue ADA, 34392 Montpellier, France
D. Auvergne	Laboratoire d'Informatique, de Robotique et de, Microélectronique deMontpellier, LIRMM UMR CNRS 9928, University Montpellier II, 161 Rue ADA, 34392 Montpellier, France

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 44, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/224081.224104 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J.EFishburnand A.E.Dunlop :"TILOS: A posynomial programming approach to transistor sizing", Proc. 1985 Int. Conf. on Computer Aided Design, pp 326-328, Nov. 1985.
	2	S.Sapatnekar, V.B.Rao,P.M.Vaidya and S.M. Kang: "An exact solution to the transistor sizingproblem for CMOS circuits using convex optimization", IEEE Trans.on CAD, vol. 12, n~ll, pp 1621-1633, Nov.1993.
	3	K. Chaudhary , M. Pedram, A near optimal algorithm for technology mapping minimizing area under delay constraints, Proceedings of the 29th ACM/IEEE conference on Design automation, p.492-498, June 08-12, 1992, Anaheim, California, United States
	4	A.E Chandrasakan, S.Sheng, R.W. Brodersen :"Low power CMOS digital design", IEEE J. Solid State Circuits, vol. 27, pp. 473-484, april 1992.
	5	D.Liu, C.Svensson : "Trading speed for low power by choice of supply and threshold voltages", IEEE J. Solid State Circuits, vol 28, pp. 1 0-17, jan. 1993.
	6	ESEVanoostende, ESix, J.Vandewalle, H.J. de Man: "Estimation of typical power of synchronous CMOS circuits using a hierarchy ofsimulator", IEEE J. Solid State Circuits, vol 28, pp 26-39, Jan. 1993.
	7	C.Y.Tsui, M.Pedram, A.M. Despain : "Power efficient technology decomposition and mapping under an extended power consumption model", IEEE trans, on CAD, vol. 13, n~9, pp. 1110-1122, sept.1994.
	8	H.J.M. Veendrick :"Short circuit power dissipation of static CMOS circuitry and its impact on the design of buffer circuits", IEEEJ. Solid State Circuits, vol SC-19, pp. 468-473, aug.1984.
	9	N.Hedenstierna, K.Jeppson : "CMOS circuit speed and buffer optimization", IEEE trans, on CAD, vol.6, pp.270-281, mar. 1987.
	10	A.J.A1-Khalili, Y.Zhu, D.A1-Khalili : "A module generator for optimized CMOS buffers", IEEE Trans. on CAD, vol. 9, pp. 1028-1046, oct. 1990.
	11	S.R.Vemuru, N.Scheinberg : "Short circuit power dissipation for CMOS logic gates", IEEE Trans. on circuits and systems (fundamental theory and applications), vol. 41, n~ll, pp 762-764, nov. 1994.
	12	S.M.Kang :"Accurate simulation of power dissipation in VLSI circuits", IEEE J. Solid State Circuits, vol. SC-21, pp. 889-891, oct. 1986.
	13	G.Y.Yacoub, W.H.Ku :"An enhanced technique for simulating short-circuit power dissipation", IEEE J. Solid State Circuits, vol.24, pp. 844-847, june 1989
	14	D.Deschacht, M.Robert, D.Auvergne:"Explicit formulation of delays on CMOS data path", IEEE J. Solid State Circuits, vol. 23, n~ 5, pp. 1257-1264, oct.1988.
	15	D.Auvergne, N.Azemard, D.Deschacht, M.Robert : "Input waveform slope effects in CMOS delays", IEEE J. Solid State Circuits, vol. 26, n~ 6, pp. 1588-1590, dec.1990.
	16	EColl, M.Robert, X.Regnier, D.Auvergne :"Process characterisation with dynamic test structures", Electronics Letters, vol.29, n~ 20, pp.1764-1766, sept. 1993.

CITED BY 6

	Massoud Pedram , Hirendu Vaishnav, Power Optimization in VLSI Layout: A Survey, Journal of VLSI Signal Processing Systems, v.15 n.3, p.221-232, March 1997
	L. Bisdounis , O. Koufopavlou , S. Nikolaidis, Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices, Proceedings of the 1996 international symposium on Low power electronics and design, p.189-192, August 12-14, 1996, Monterey, California, United States
	S. Turgis , J. M. Daga , J. M. Portal , D. Auvergne, Internal power modelling and minimization in CMOS inverters, Proceedings of the 1997 European conference on Design and Test, p.603, March 17-20, 1997
	L. Bisdounis , S. Nikolaidis , O. Koufopavlou, Analytical Model for the CMOS Short-Circuit Power Dissipation, Integrated Computer-Aided Engineering, v.5 n.2, p.129-140, April 1998
	S. Turgis , N. Azemard , D. Auvergne, Design and selection of buffers for minimum power-delay product, Proceedings of the 1996 European conference on Design and Test, p.224, March 11-14, 1996
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996