Analysis of glitch power dissipation in CMOS ICs

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Analysis of glitch power dissipation in CMOS ICs

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 123 - 128

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

M. Favalli	DEIS, University of Bologna, Viale Risorgimento, 2, 40136 Bologna, Italy
L. Benini	CIS, Stanford University, Stanford CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 39, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Chandrakasan et al., J. of Solid State Circuits, vol. 27, no. 4, pp. 473 -484, 1992.
	2	F. Najm et al., in Proc. of ICCAD, pp. 204- 207, 1988.
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	5	J. Lin et al., in Proc. of DAC, pp. 304- 309, 1994.
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	8	S. Chowdury et al., Trans. on CAD, vol. 9, no. 6, pp. 642- 654, 1990.
	9	L. Benini et al., in Proc. of DAC, pp. 354- 360, 1993.
	10	L. Benini et al., in Int. Syrup. on Low Power Design, pp. 27 - 32, 1994.
	11	H. J. M. Veendrick, J. of Solid State Circuits, vol. SC- 19, pp. 468- 473, August 1984.

CITED BY 13

	Hyeonmin Lim , Kyungsoo Lee , Youngjin Cho , Naehyuck Chang, Flip-flop insertion with shifted-phase clocks for FPGA power reduction, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.335-342, November 06-10, 2005, San Jose, CA
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Glitch analysis and reduction in register transfer level power optimization, Proceedings of the 33rd annual conference on Design automation, p.331-336, June 03-07, 1996, Las Vegas, Nevada, United States
	D. Rabe , W. Nebel, New approach in gate-level glitch modelling, Proceedings of the conference on European design automation, p.66-71, September 1996, Geneva, Switzerland
	R. S. Bajwa , N. Schumann , H. Kojima, Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP, Proceedings of the 1997 international symposium on Low power electronics and design, p.137-142, August 18-20, 1997, Monterey, California, United States
	D. Rabe , G. Jochens , L. Kruse , W. Nebel, Power-simulation of cell based ASICs: accuracy-and performance trade-offs, Proceedings of the conference on Design, automation and test in Europe, p.356-361, February 23-26, 1998, Le Palais des Congrés de Paris, France
	R. S. Bajwa , N. Schumann , H. Kojima, Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP, Proceedings of the 1997 international symposium on Low power electronics and design, p.137-142, August 18-20, 1997, Monterey, California, United States
	Daniel Brand , Chandu Visweswariah, Inaccuracies in power estimation during logic synthesis, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.388-394, November 10-14, 1996, San Jose, California, United States
	Steven M. Nowick , Michael Theobald, Synthesis of low-power asynchronous circuits in a specified environment, Proceedings of the 1997 international symposium on Low power electronics and design, p.92-95, August 18-20, 1997, Monterey, California, United States
	D. Rabe , W. Nebel, Short circuit power consumption of glitches, Proceedings of the 1996 international symposium on Low power electronics and design, p.125-128, August 12-14, 1996, Monterey, California, United States
	Ki-Seok Chung , Taewhan Kim , C. L. Liu, G-vector: A New Model for Glitch Analysis in Logic Circuits, Journal of VLSI Signal Processing Systems, v.27 n.3, p.235-251, March 1, 2001
	P. Schneider , S. Krishnamoorthy, Effects of correlations on accuracy of power analysis—an experimental study, Proceedings of the 1996 international symposium on Low power electronics and design, p.113-116, August 12-14, 1996, Monterey, California, United States
	Sangjin Hong , Shu-Shin Chin, Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications, Journal of VLSI Signal Processing Systems, v.40 n.2, p.239-259, June 2005
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996