CMOS dynamic power estimation based on collapsible current source transistor modeling

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CMOS dynamic power estimation based on collapsible current source transistor modeling

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 111 - 116

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Abelardo Pardo	University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO
R. Iris Bahar	University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO
Srilatha Manne	University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO
Peter Feldmann	AT&T Bell Laboratories, 600 Mountain View, Murray Hill, NJ
Gary D. Hachtel	University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO
Fabio Somenzi	University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 8, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. P. Chandrakasan, S. Sheng, and R. W. Broderson, "Low-power CMOS digital design," IEEE Jour. Solid State Circ., pp. 473-484, Apr. 1992.
	2	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	3	Richard Burch , Farid Najm , Ping Yang , Dale Hocevar, Pattern-independent current estimation for reliability analysis of CMOS circuits, Proceedings of the 25th ACM/IEEE conference on Design automation, p.294-299, June 12-15, 1988, Atlantic City, New Jersey, United States
	4	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
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	6	B. R. Chawla, H. K. Gummel, and P. Kozak, "Motis - an mos timing simulator," IEEE Transactions on Circuits and Systems, vol. 22, pp. 901-910, Dec. 1975.
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	8	Russell Kao , Mark Horowitz, Piecewise linear models for Rsim, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.753-758, November 07-11, 1993, Santa Clara, California, United States
	9	F. Rouatbi , B. Haroun , A. J. Al-Khalili, Power estimation tool for sub-micron CMOS VLSI circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.204-209, November 1992, Santa Clara, California, United States
	10	M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures. Princeton University Press, 1992.