Activity-sensitive architectural power analysis for the control path

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Activity-sensitive architectural power analysis for the control path

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 93 - 98

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Paul E. Landman	Integrated Systems Laboratory, Texas Instruments, Dallas, Texas
Jan M. Rabaey	EECS Department, University of California, Berkeley, Berkeley, California

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 19, Citation Count: 18

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Deng, "Power Analysis for CMOS/BiCMOS Circuits," 1994 International Workshop on Low Power Design, Napa Valley, CA, pp. 3-8, April 1994.
	2	P. Landman and J. Rabaey, "Black-Box Capacitance Models for Architectural Power Analysis," 1994 International Workshop on Low Power Design, pp. 165-170, April 1994.
	3	Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
	4	Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
	5	K. M~ller-Glaser, K. Kirsch, and K. Neusinger, "Estimating Essential Design Characteristics to Support Project Planning for ASIC Design Management," IEEE International Conference on Computer-Aided Design '91, pp. 148-151, Nov. 1991.
	6	C. Svensson and D. Liu, "A Power Estimation Tool and Prospects of Power Savings in CMOS VLSI Chips," 1994 International Workshop on Low-Power Design,p. 171-176, Apr. 1994.
	7	A. Salz , M. Horowitz, IRSIM: an incremental MOS switch-level simulator, Proceedings of the 26th ACM/IEEE conference on Design automation, p.173-178, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74412]
	8	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	9	Robert W. Brodersen, Anatomy of a Silicon Compiler, Kluwer Academic Publishers, Norwell, MA, 1992
	10	Paul Eric Landman, Low-power architectural design methodologies, University of California at Berkeley, Berkeley, CA, 1995

CITED BY 18

	S. Katkoori , R. Vemuri, Simulation based architectural power estimation for PLA-based controllers, Proceedings of the 1996 international symposium on Low power electronics and design, p.121-124, August 12-14, 1996, Monterey, California, United States
	Chi-Ying Tsui , Kai-Keung Chan , Qing Wu , Chih-Shun Ding , Massoud Pedram, A power estimation framework for designing low power portable video applications, Proceedings of the 34th annual conference on Design automation, p.421-424, June 09-13, 1997, Anaheim, California, United States
	Qinru Qiu , Qing Wu , Massoud Pedram , Chih-Shun Ding, Cycle-accurate macro-models for RT-level power analysis, Proceedings of the 1997 international symposium on Low power electronics and design, p.125-130, August 18-20, 1997, Monterey, California, United States
	Rita Yu Chen , Robert M. Owens , Mary Jane Irwin , R. S. Bajwa , Raminder S. Bajwa, Validation of an architectural level power analysis technique, Proceedings of the 35th annual conference on Design automation, p.242-245, June 15-19, 1998, San Francisco, California, United States
	Cheng-Ta Hsieh , Qing Wu , Chih-Shun Ding , Massoud Pedram, Statistical sampling and regression analysis for RT-level power evaluation, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.583-588, November 10-14, 1996, San Jose, California, United States
	Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin, Energy characterization based on clustering, Proceedings of the 33rd annual conference on Design automation, p.702-707, June 03-07, 1996, Las Vegas, Nevada, United States
	Rita Yu Chen , Mary Jane Irwin , Raminder S. Bajwa, Architecture-level power estimation and design experiments, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.1, p.50-66, Jan. 2001
	Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin , Rita Chen , Debashree Ghosh, Techniques for low energy software, Proceedings of the 1997 international symposium on Low power electronics and design, p.72-75, August 18-20, 1997, Monterey, California, United States
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.158-165, November 10-14, 1996, San Jose, California, United States
	E. Musoll , J. Cortadella, Scheduling and resource binding for low power, Proceedings of the 8th international symposium on System synthesis, p.104-109, September 13-15, 1995, Cannes, France
	Diana Marculescu , Radu Marculescu , Massoud Pedram, Theoretical bounds for switching activity analysis in finite-state machines, Proceedings of the 1998 international symposium on Low power electronics and design, p.36-41, August 10-12, 1998, Monterey, California, United States
	J. Carletta , C. A. Papachristou , M. Nourani, Detecting undetectable controller faults using power analysis, Proceedings of the conference on Design, automation and test in Europe, p.723-728, March 27-30, 2000, Paris, France
	Enric Musoll , Jordi Cortadella, Register-Transfer Level Transformations for Low-Power Data-Paths, Integrated Computer-Aided Engineering, v.5 n.4, p.315-332, December 1998
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, High-level macro-modeling and estimation techniques for switching activity and power consumption, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.538-557, August 2003
	Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States
	Mehrdad Nourani , Joan Carletta , Christos Papachristou, Integrated test of interacting controllers and datapaths, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.401-422, July 2001
	Farid N. Najm, Power estimation techniques for integrated circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.492-499, November 05-09, 1995, San Jose, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996