Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers

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Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 75 - 80

Year of Publication: 1995

ISBN:0-89791-744-8

Author

Anthony Correale, Jr.

PowerPC Integrated Solutions, IBM Microelectronics, RTP, NC

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 34, Citation Count: 6

Additional Information:

references cited by index terms peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	IBM PowerPC 403GA 32-Bit RISC Embedded Controller data sheet Document No.MPR403DSU-01 09.02.94
	2	CMOS5L Design Manual, IBM Engineering Specification 02G1508
	3	A.RChandrakasan,S.Sheng and R.W.Brodersen, "Low- Power CMOS Design," in IEEE Journal of Solid State Circuits, Vol. 27, NO. 4, April 1992, pg.475
	4	E. B. Eichelberger , T. W. Williams, A logic design structure for LSI testability, Proceedings of the 14th conference on Design automation, p.462-468, January 1977
	5	Anthony Correale, Jr., "Power Reduction Technique for Chips Using Common I/O'", in IBM Technical Disclosure Bulletin, Vol. 37, No. 01, January 1994
	6	Anthony Correale, Jr., "Design considerations of a static LSSD polarity hold latch pair", in IBM Journal of Research and Development, Vol.28, No. 4, July 1984, pp.370-377

CITED BY 6

	William E. Dougherty , Donald E. Thomas, Modeling and automating selection of guarding techniques for datapath elements, Proceedings of the 1999 international symposium on Low power electronics and design, p.182-187, August 16-17, 1999, San Diego, California, United States
	M. Münch , B. Wurth , R. Mehra , J. Sproch , N. Wehn, Automating RT-level operand isolation to minimize power consumption in datapaths, Proceedings of the conference on Design, automation and test in Europe, p.624-633, March 27-30, 2000, Paris, France
	Hans M. Jacobson, Improved clock-gating through transparent pipelining, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	A. Chattopadhyay , B. Geukes , D. Kammler , E. M. Witte , O. Schliebusch , H. Ishebabi , R. Leupers , G. Ascheid , H. Meyr, Automatic ADL-based operand isolation for embedded processors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	N. Banerjee , A. Raychowdhury , K. Roy , S. Bhunia , H. Mahmoodi, Novel low-overhead operand isolation techniques for low-power datapath synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.9, p.1034-1039, September 2006
	K. J. Nowka , G. D. Carpenter , B. C. Brock, The design and application of the PowerPC 405LP energy-efficient system-on-a-chip, IBM Journal of Research and Development, v.47 n.5-6, p.631-639, September 2003