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Cache design trade-offs for power and performance optimization: a case study
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents
Dana Point, California, United States
Pages: 63 - 68  
Year of Publication: 1995
ISBN:0-89791-744-8
Authors
Ching-Long Su  Advanced Computer Architecture Laboratory, University of Southern California
Alvin M. Despain  Advanced Computer Architecture Laboratory, University of Southern California
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 133,   Citation Count: 85
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
J. Bunda, W.C. Athas, and D. Fussell, "Evaluating Power Implication of CMOS Microprocessor Design Decisions," In Proc. of the 1994 International Workshop on Low Power Design, April 1994.
 
2
B. Burgress, et al., "The PowerPCTM603 Microprocessor: A High Performance, Low Power, Superscalar RISC processor," In Proc. oflEEE COMPCON, February 1994.
 
3
S.B. Furber, et al.,"AMULETI: A Microppipelined ARM," In Proc. of lEEE COMPCON, February 1994.
 
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A.J. Smith, "A Comparative Study of Set Associative Memory Mapping Algorithms and Their Use for Cache and Memory," In IEEE Transactions on Software Engineering, Vol. 4, No. 2, March 1978.
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13
T. Wada, S. Rajan, S.A. Przybylski, "An Analytical Access Time Model for On-Chip Cache Memories," IEEE Journal of Solid-State Circuits, Vol. 27, No. 8, Aug., 1992.
 
14
S. Wilton, N. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Research Report 93/5, Digital, June, 1994.

CITED BY  86
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Collaborative Colleagues:
Ching-Long Su: colleagues
Alvin M. Despain: colleagues

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