Reducing the frequency of tag compares for low power I-cache design

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Reducing the frequency of tag compares for low power I-cache design

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 57 - 62

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Ramesh Panwar	4731G Boelter Hall, Computer Science Department, University of California, Los Angeles, California
David Rennels	4731G Boelter Hall, Computer Science Department, University of California, Los Angeles, California

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 23, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Robert F. Cmelik , David Keppel, Shade: A Fast Instruction Set Simulator for Execution Profiling, Sun Microsystems, Inc., Mountain View, CA, 1993
	2	Ellis Horowitz , Sartaj Sahni, Computing Partitions with Applications to the Knapsack Problem, Journal of the ACM (JACM), v.21 n.2, p.277-292, April 1974 [doi>10.1145/321812.321823]
	3	Liu, D. and Svensson, C., "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, 29, 663-670, 1994.
	4	Pentium Processor User's Manual. Mt. Prospect, IL: Intel, 1993.
	5	D. N. Pnevmatikatos , G. S. Sohi, Guarded execution and branch prediction in dynamic ILP processors, Proceedings of the 21ST annual international symposium on Computer architecture, p.120-129, April 18-21, 1994, Chicago, Illinois, United States
	6	Shlomo Weiss , James E. Smith, IBM Power and PowerPC, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1994
	7	CORPORATE SPARC International, Inc., The SPARC architecture manual (version 9), Prentice-Hall, Inc., Upper Saddle River, NJ, 1994

CITED BY 12

	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Youtao Zhang , Jun Yang, Low cost instruction cache designs for tag comparison elimination, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Youtao Zhang , Jun Yang, Reducing I-cache energy of multimedia applications through low cost tag comparison elimination, Journal of Embedded Computing, v.1 n.4, p.461-470, December 2005
	Tohru Ishihara , Farzan Fallah, A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors, Proceedings of the conference on Design, Automation and Test in Europe, p.358-363, March 07-11, 2005
	Peter Petrov , Alex Orailoglu, Energy frugal tags in reprogrammable I-caches for application-specific embedded processors, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Koji Inoue , V. G. Moshnyaga , K. Murakami, A history-based I-cache for low-energy multimedia applications, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Emmett Witchel , Sam Larsen , C. Scott Ananian , Krste Asanović, Direct addressed caches for reduced power consumption, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Tohru Ishihara , Farzan Fallah, A non-uniform cache architecture for low power system design, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Ahmad Zmily , Christos Kozyrakis, A low power front-end for embedded processors using a block-aware instruction set, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
	I. Kadayif , A. Sivasubramaniam , M. Kandemir , G. Kandiraju , G. Chen, Optimizing instruction TLB energy using software and hardware techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.229-257, April 2005
	Chuanjun Zhang , Frank Vahid , Jun Yang , Walid Najjar, A way-halting cache for low-energy high-performance systems, ACM Transactions on Architecture and Code Optimization (TACO), v.2 n.1, p.34-54, March 2005
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000