Energy optimization of multi-level processor cache architectures

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Energy optimization of multi-level processor cache architectures

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents

Dana Point, California, United States

Pages: 45 - 49

Year of Publication: 1995

ISBN:0-89791-744-8

Authors

Uming Ko	Texas Instruments Incorporated, P. O. Box 655303, M/S 8316, Dallas, TX
Poras T. Balsara	Department of Electrical Engineering, University of Texas at Dallas, P. O. Box 830688, Richardson, TX
Ashwini K. Nanda	Texas Instruments Incorporated, P. O. Box 655303, M/S 8316, Dallas, TX

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 31, Citation Count: 10

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Date, N. Shibata, S.Mutoh, and J. Yamada, "IV 30MHz Memory-Macrocell-Circuit Technology with a 0.5urn Multi-Threshold CMOS," Proceedings of the 1994 Symposium on Low Power Electronics, San Diego, CA, pp. 90-91, Oct. 1994.
	2	S. T. Chu, "A 25 ns Low Power Full-CMOS 1Mbit (128Kx8) SRAM," Journal of Solid State Circuits, vol. 23, pp. 1078-1084, Oct. 1988.
	3	D.T. Wong, "A 11 ns 8Kx18 CMOS Static RAM with 0.5 ~m devices," Journal of Solid State Circuits, vol. 23, pp. 1095-1103, Oct. 1988.
	4	B. Amrutur, and M. Horowitz, "Techniques to Reduce Power in Fast Wide Memories," Proceedings of the 1994 Symposium on Low Power Electronics, San Diego, CA, pp. 92-93, Oct. 1994.
	5	K. Itoh, K. Sasaki, and Y. Nakagome, "Trends in Low- Power RAM Circuit Technologies," Proceedings of the 1994 Symposium on Low Power Electronics, San Diego,
	6	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
	7	Jeffrey D. Gee , Mark D. Hill , Dionisios N. Pnevmatikatos , Alan Jay Smith, Cache Performance of the SPEC92 Benchmark Suite, IEEE Micro, v.13 n.4, p.17-27, July 1993 [doi>10.1109/40.229711]

CITED BY 10

	Rui Min , Wen-Ben Jone , Yiming Hu, Location cache: a low-power L2 cache system, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Patrick Hicks , Matthew Walnock , Robert Michael Owens, Analysis of power consumption in memory hierarchies, Proceedings of the 1997 international symposium on Low power electronics and design, p.239-242, August 18-20, 1997, Monterey, California, United States
	Vasily G. Moshnyaga, Reducing cache engery through dual voltage supply, Proceedings of the 2001 conference on Asia South Pacific design automation, p.302-305, January 2001, Yokohama, Japan
	Koji Inoue , Tohru Ishihara , Kazuaki Murakami, Way-predicting set-associative cache for high performance and low energy consumption, Proceedings of the 1999 international symposium on Low power electronics and design, p.273-275, August 16-17, 1999, San Diego, California, United States
	Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	Kun Zhang , Tao Zhang , Santosh Pande, Binary translation to improve energy efficiency through post-pass register re-allocation, Proceedings of the 4th ACM international conference on Embedded software, September 27-29, 2004, Pisa, Italy
	Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States
	Johnson Kin , Munish Gupta , William H. Mangione-Smith, Filtering Memory References to Increase Energy Efficiency, IEEE Transactions on Computers, v.49 n.1, p.1-15, January 2000
	Dirk Grunwald, Micro-architecture design and control speculation for energy reduction, Power aware computing, Kluwer Academic Publishers, Norwell, MA, 2002
	Lode Nachtergaele , Francky Catthoor , Chidamber Kulkarni, Random-Access Data Storage Components in Customized Architectures, IEEE Design & Test, v.18 n.3, p.40-54, May 2001