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Unifying carry-sum and signed-digital number representations for low power
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1995 international symposium on Low power design table of contents
Dana Point, California, United States
Pages: 15 - 20  
Year of Publication: 1995
ISBN:0-89791-744-8
Authors
Chetana Nagendra  Department of Computer Science and Eng., The Pennsylvania State University, University Park
Robert Michael Owens  Department of Computer Science and Eng., The Pennsylvania State University, University Park
Mary Jane Irwin  Department of Computer Science and Eng., The Pennsylvania State University, University Park
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. Avizienis. Signed-digit number representation for fast parallel arithmetic. IRE Trans. on Electronic Computers, page 389, 1961.
 
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Meta-Software. ItSPICE User's Manual version It92. Campbell, CA, 1992. Meta-Software, Inc., 1300 White Oaks Road, Campbell, CA 95008.
 
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C. Nagendra, R. M. Owens, and M. J. Irwin. Low Power Tradeoffs in Signal Processing Hardware Primitives. In IEEE Workshop on VLSI Signal Processing, pages 276-285, Oct 1994.
 
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Collaborative Colleagues:
Chetana Nagendra: colleagues
Robert Michael Owens: colleagues
Mary Jane Irwin: colleagues

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