Multiple FPGA partitioning with performance optimization

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Multiple FPGA partitioning with performance optimization

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays table of contents

Monterey, California, United States

Pages: 146 - 152

Year of Publication: 1995

ISBN:0-89791-743-X

Authors

Kalapi Roy-Neogi	Dept. of Electrical Engineering, FT-10, University of Washington, Seattle, WA
Carl Sechen	Dept. of Electrical Engineering, FT-10, University of Washington, Seattle, WA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 41, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Kuznar, F. Brglez, and K. Kozminski, "Partitioning Digital Circuits for Implementation in Multiple FPGA ICs," Technical Report TR93-03, MCNC, 1993.
	2	Nam Sung Woo , Jaeseok Kim, An efficient method of partitioning circuits for multiple-FPGA implementation., Proceedings of the 30th international conference on Design automation, p.202-207, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164669]
	3	James Hwang , Abbas El Gamal, Optimal replication for min-cut partitioning, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.432-435, November 1992, Santa Clara, California, United States
	4	G. Saucier , D. Brasen , J. P. Hiol, Partitioning with cone structures, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.236-239, November 07-11, 1993, Santa Clara, California, United States
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	7	Prashant Sawkar , Donald Thomas, Performance directed technology mapping for look-up table based FPGAs, Proceedings of the 30th international conference on Design automation, p.208-212, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164672]
	8	Jason Cong , Yuzheng Ding, On area/depth trade-off in LUT-based FPGA technology mapping, Proceedings of the 30th international conference on Design automation, p.213-218, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164675]
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	12	K. Perry, "Eliminating Barriers to FPGA use by Timing Driven Partitioning," Electronic Engineering, Jan. 1993, pp. 41- 44.
	13	"Concept Silicon Partitions your Design onto Multiple FPGAs," Integrated Circuit Applications Pamphlet, InCA Inc., Campbell CA 95008, 1992.
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	16	Kalapi Roy , Carl Sechen, A timing driven N-way chip and multi-chip partitioner, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.240-247, November 07-11, 1993, Santa Clara, California, United States
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CITED BY 9

	Young-Su Kwon , Chong-Min Kyung, ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.861-864, July 2005
	S. A. Senouci , A. Amoura , H. Krupnova , G. Saucier, Timing driven floorplanning on programmable hierarchical targets, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.85-92, February 22-25, 1998, Monterey, California, United States
	Frank Vahid, I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.27-34, February 09-11, 1997, Monterey, California, United States
	Wai-Kei Mak, Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead, Proceedings of the 2001 international symposium on Physical design, p.100-105, April 01-04, 2001, Sonoma, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.638-643, November 10-14, 1996, San Jose, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Multiway FPGA partitioning by fully exploiting design hierarchy, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.34-50, Jan. 2000
	Meenakshi Kaul , Ranga Vemuri, Design-Space Exploration for Block-Processing Based TemporalPartitioning of Run-Time Reconfigurable Systems, Journal of VLSI Signal Processing Systems, v.24 n.2-3, p.181-209, Mar. 2000
	Frank M. Johannes, Partitioning of VLSI circuits and systems, Proceedings of the 33rd annual conference on Design automation, p.83-87, June 03-07, 1996, Las Vegas, Nevada, United States
	Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Shankar Radhakrishnan , Sujatha Sundaraman , Satish Ganesan , Awartika Pandey , Preetham Lakshmikanthan, Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems, Physica-Verlag GmbH, Heidelberg, Germany, 2001