On designing ULM-based FPGA logic modules

ABSTRACT

In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FP-GAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrates the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits.

REFERENCES

• 1: X. Chen and X. Wu. Derivation of universal logic modules, for n > 3, by algebraic means. IEE Proc., 128(5):205-211, September 1981.
• 2: Silvia Ercolani , Giovanni De Micheli, Technology mapping for electrically programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.234-239, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127671]
• 3: E.M. Sentovich et al. SIS' A system for sequential circuit synthesis. Technical Report UCB/ERL M92/41, Dept. of Electrical Engg. and Computer Science, Univ. of California, Berkeley, CA 94720, 1992.
• 4: K. Keutzer. Impact of library size on the quality of automated synthesis. In Proceedings of ICCAD, pages 120-123. ACM/IEEE, 1990.
• 5: Chih-chang Lin , Malgorzata Marek-Sadowska , Duane Gatlin, Universal logic gate for FPGA design, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.164-168, November 06-10, 1994, San Jose, California, United States
• 6: F. Mailhot and G. De Micheli. Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. IEEE Trans. CAD/ICAS, 12(5)'599-620, May 1993.
• 7: J. Mohnke and S. Malik. Permutation and phase independent Boolean comparison. In Proceedings of EDAC, 1993.
• 8: F. P. Preparata and D.E. Muller. Generation of near-optimal universal boolean functions. JCCS, 4:93-102, April 1970.
• 9: Shashidhar Thakur , Martin D. F. Wong, On Designing ULM-Based FPGA Logic Modules, University of Texas at Austin, Austin, TX, 1994

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays

General Terms:
Algorithms, Design, Experimentation, Performance, Theory